Design and Implementation of Communication Scheme between Ethernet and Multi-Serial Port

With the development of aerospace technology, the flight control system is getting more and more important for a UAV (Unmanned Aerial Vehicle) flying safely and efficiently. For collecting the experimental data without delay, this paper briefly reviews the design of the communication scheme, and provides the implemented results. Through using the controller LPC1768 to expand the serial port, and the Ethernet controller DP83848 to complete the communication by UDP protocol, it turns out that this method is able to reach the real-time requirements of the UAV semi-physical simulation.

Design of Equipment Power Remote Control System Based on Ethernet

A network power control system was designed in the paper based on MCU STM32 in order to realize network control to the industrial site power equipment. Software and hardware design scheme of the system were given. STM32F103 chip was used as the main controller in the system and ENC28J60 chip as the Ethernet controller to connect network, the μIP protocol stack was used for network data communication. Network power control test experiment was carried out, the result showed that it can control the equipment power remotely, and can receive real-time information data of the industrial field through Ethernet.Compared with the traditional power control system, this system has the characteristics of intelligence, integration and remote.

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.