Algorithms and Parallel VLSI Architectures III
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Efficient VLSI Architecture for Residue to Binary Converter

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50010-7 ◽

1995 ◽

pp. 109-115

Author(s):

G.C. Cardarilli ◽

R. Lojacono ◽

M. Re ◽

M. Salerno

Keyword(s):

Vlsi Architecture

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Instruction-Level Parallelism in Asynchronous Processor Architectures

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50018-1 ◽

1995 ◽

pp. 203-214 ◽

Author(s):

D.K. Arvind ◽

V.E.F. Rebello

Keyword(s):

Instruction Level Parallelism ◽

Processor Architectures ◽

Level Parallelism

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Subspace Methods in System Identification and Source Localization

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50002-8 ◽

1995 ◽

pp. 13-23

Author(s):

P.A. Regalia

Keyword(s):

System Identification ◽

Source Localization ◽

Subspace Methods

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Parallel Implementation of the Double Bracket Matrix Flow for Eigenvalue-Eigenvector Computation and Sorting

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50008-9 ◽

1995 ◽

pp. 85-96

Author(s):

N. Saxena ◽

J.J. Clark

Keyword(s):

Parallel Implementation ◽

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Uniformisation Techniques for Reducible Integral Recurrence Equations

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50025-9 ◽

1995 ◽

pp. 283-294 ◽

Author(s):

L. Rapanotti ◽

G.M. Megson

Keyword(s):

Recurrence Equations

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Adaptive Approximate Rotations for Computing the Symmetric EVD

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50007-7 ◽

1995 ◽

pp. 73-84

Author(s):

J. Götze ◽

G.J. Hekstra

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On Factors Limiting the Generation of Efficient Compiler-Parallelized Programs

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50029-6 ◽

1995 ◽

pp. 331-339

Author(s):

M.R. Werth ◽

P. Feautrier

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A Scalable Design for Dictionary Machines

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50013-2 ◽

1995 ◽

pp. 143-154 ◽

Author(s):

T. Duboux ◽

A. Ferreira ◽

M. Gastaldo

Keyword(s):

Scalable Design

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Convex Exemplar Systems

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50020-x ◽

1995 ◽

pp. 227-234

Author(s):

J. Van Kats

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Modelling the 2-D FCT on a Multiprocessor System

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50021-1 ◽

1995 ◽

pp. 235-244

Author(s):

C.A. Christopoulos ◽

A.N. Skodras ◽

J. Cornelis

Keyword(s):

Multiprocessor System

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