2007 IFIP International Conference on Very Large Scale Integration
Latest Publications

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Published By IEEE

9781424417094, 9781424417100

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Power invariant secure IC design methodology using reduced complementary dynamic and differential logic

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402463 ◽

2007 ◽

Cited By ~ 7

Author(s):

Vijay Sundaresan ◽

Srividhya Rammohan ◽

Ranga Vemuri

Keyword(s):

Design Methodology ◽

Ic Design ◽

Power Invariant

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Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402480 ◽

2007 ◽

Author(s):

Vyas Krishnan ◽

Srinivas Katkoori

Keyword(s):

High Level Synthesis ◽

High Level

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Efficient timing closure with a transistor level design flow

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402520 ◽

2007 ◽

Author(s):

Cristiano Lazzari ◽

Cristiano Santos ◽

Adriel Ziesemer ◽

Lorena Anghel ◽

Ricardo Reist

Keyword(s):

Design Flow ◽

Timing Closure ◽

Level Design

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AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402477 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yikui (Jen) Dong ◽

Steve Howard ◽

Freeman Zhong ◽

Scott Lowrie ◽

Ken Paradis ◽

...

Keyword(s):

High Speed ◽

Coupling Strategy

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Parametric structure-preserving model order reduction

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402468 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jorge Fernandez Villena ◽

Wil H. A. Schilders ◽

L. Miguel Silveira

Keyword(s):

Model Order Reduction ◽

Order Reduction ◽

Model Order ◽

Structure Preserving

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A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402507 ◽

2007 ◽

Cited By ~ 6

Author(s):

M. Sudhakar ◽

R.V. Kamala ◽

M.B. Srinivas

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A low-power deblocking filter architecture for H.264 advanced video coding

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402496 ◽

2007 ◽

Cited By ~ 1

Author(s):

Jaemoon Kim ◽

Sangkown Na ◽

Chong-Min Kyung

Keyword(s):

Low Power ◽

Video Coding ◽

Deblocking Filter ◽

Filter Architecture ◽

Advanced Video Coding

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Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 μm CMO S

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402505 ◽

2007 ◽

Author(s):

Run Chen ◽

Liyuan Liu ◽

Dongmei Li ◽

Zhihua Wang

Keyword(s):

Custom Design

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Neuromorphic building blocks for adaptable cortical feature maps

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402464 ◽

2007 ◽

Cited By ~ 2

Author(s):

C. M. Markan ◽

Priti Gupta

Keyword(s):

Building Blocks ◽

Feature Maps

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Use of gray decoding for implementation of symmetric functions

2007 IFIP International Conference on Very Large Scale Integration ◽

10.1109/vlsisoc.2007.4402467 ◽

2007 ◽

Cited By ~ 5

Author(s):

Osnat Keren ◽

Ilya Levin ◽

Radomir S. Stankovic

Keyword(s):

Symmetric Functions

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2007 IFIP International Conference on Very Large Scale IntegrationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Power invariant secure IC design methodology using reduced complementary dynamic and differential logic

Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis

Efficient timing closure with a transistor level design flow

AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

Parametric structure-preserving model order reduction

A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC

A low-power deblocking filter architecture for H.264 advanced video coding

Full custom design of a three-stage amplifier with 5500MHz·pF/mW Performance in 0.18 μm CMO S

Neuromorphic building blocks for adaptable cortical feature maps

Use of gray decoding for implementation of symmetric functions

2007 IFIP International Conference on Very Large Scale Integration
Latest Publications