With increasing complexity of data processing applications, there is a huge demand for high storage compact memories. It is highly desirable that memories have low access time and consume less power. Processing of data along with parallel memory storage has proved to be more efficient than serial operation. One such approach to paralleling processing is the concept of Embedded Memories. By inserting the logic within architecture of the flip-flop, the chip area can be reduced. Also, through means of Conditional Shut-down, the power consumption can be reduced.
In this paper, we propose a modified dual dynamic hybrid node Embedded Logic D-Flip flop architecture. The work is based on DSCH 3.5 and Microwind 3.5 tools. We have simulated the design for 90nm, 65nm and 45nm technology respectively. Compared to the previous architectures, we have obtained a reduction in propagation delay by 15.38% and reduction in power consumption by 32.69%. Further, we have designed a 4X4 memory using our proposed Embedded Logic Flip Flop. The embedded memory finds applications in highly complex data processing applications, scan test circuits etc