scholarly journals A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power

2018 ◽  
Vol 10 (5-6) ◽  
pp. 562-569 ◽  
Author(s):  
M.H. Eissa ◽  
A. Malignaggi ◽  
M. Ko ◽  
K. Schmalz ◽  
J. Borngräber ◽  
...  

AbstractThis work presents a fully differential wideband and low power 240 GHz multiplier-by-8 chain, manufactured in IHP's 130 nm SiGe:C BiCMOS technology with fT/fmax = 300/500 GHz. A single ended 30 GHz input signal is multiplied by 8 using Gilbert cell-based quadrupler and doubler, and then amplified with a wideband differential 3-stage cascode amplifier. To achieve wide bandwidth and optimize for power consumption, the power budget has been designed in order to operate the frequency multipliers and the output amplifier in saturation. With this architecture the presented circuit achieves a 3 dB bandwidth of 40 GHz, meaning a relative 3 dB bandwidth of 17%, and a peak saturated output power of 0 dBm. Harmonic rejections better than 25 dB were measured for the 5th, 6th, and 7th harmonics. It dissipates 255 mW from 3 V supply which results in drain efficiency of 0.4%, while occupying 1.2 mm2. With these characteristics the presented circuit suits very well as a frequency multiplier chain for driving balanced mixers in 240 GHz transceivers for radar, communication, and sensing applications.

2014 ◽  
Vol 6 (3-4) ◽  
pp. 225-233 ◽  
Author(s):  
Thomas Jensen ◽  
Thualfiqar Al-Sawaf ◽  
Marco Lisker ◽  
Srdjan Glisic ◽  
Mohamed Elkhouly ◽  
...  

The paper presents millimeter-wave (mm-wave) signal sources using a hetero-integrated InP-on-BiCMOS semiconductor technology. Mm-wave signal sources feature fundamental frequency voltage-controlled oscillators (VCOs) in BiCMOS, which drive frequency multiplier–amplifier chains in transferred-substrate (TS) InP-DHBT technology, heterogeneously integrated on top of the BiCMOS wafer in a wafer-level bonding process. Both circuits are biased through a single set of bias pads and compact low-loss transitions from BiCMOS to InP circuits and vice versa have been developed, which allows seamless signal routing through both technologies exhibiting 0.5 dB insertion loss up to 200 GHz. One VCO operates at 82 GHz with a tuning range of 600 MHz and an output power of approximately 8 dBm. A frequency doubler combined with this VCO circuit delivers 0 dBm at 164 GHz and a frequency tripler with a similar VCO delivers −10 dBm at 246 GHz. Another hetero-integrated W-band doubler–amplifier circuit demonstrates 12.9 dBm saturated output power with 5.9 dB conversion gain at 96 GHz. A direct comparison of the TS InP-DHBT MMIC with either silicon or traditional AlN carrier substrates shows the favorable properties of the hetero-integrated process discussed here. The results demonstrate the feasibility of hetero-integrated circuits operating well above 100 GHz.


2012 ◽  
Vol 22 (4) ◽  
pp. 191-193 ◽  
Author(s):  
Debin Hou ◽  
Yong-Zhong Xiong ◽  
Wang-Ling Goh ◽  
Wei Hong ◽  
Mohammad Madihian

Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.


2018 ◽  
Vol 10 (9) ◽  
pp. 999-1010 ◽  
Author(s):  
Michele Squartecchia ◽  
Tom K. Johansen ◽  
Jean-Yves Dupuy ◽  
Virginio Midili ◽  
Virginie Nodjiadjim ◽  
...  

AbstractIn this paper, we report the analysis, design, and implementation of stacked transistors for power amplifiers realized on InP Double Heterojunction Bipolar Transistors (DHBTs) technology. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations. An evaluation of the maximum number of transistors for positive incremental power and gain is also carried out. To validate the analysis, E-band three- and four-stacked InP DHBT matched power cells have been realized for the first time as monolithic microwave integrated circuits (MMICs). For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm, and a peak power added efficiency (PAE) of 5.2% have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8%. A four-way combined three-stacked MMIC power amplifier has been implemented as well. It exhibits a linear gain of 8.1 dB, a saturated output power higher than 18 dBm, and a PAE higher than 3% at 84 GHz.


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