An improved design of combinational digital circuits with multiplexers using genetic algorithm

2013 ◽  
Author(s):  
C. K. Vijayakumari ◽  
Dileep Lukose ◽  
P Mythili ◽  
Rekha K. James
Keyword(s):  
Genetic Algorithm ◽  
Digital Circuits ◽  
Improved Design

Effectiveness of Neural Network and Genetic Algorithm in Hull Form Design

2001 ◽  
Author(s):  
M. Reaz H. Khondoker ◽  
Chowdhury Mofizur Rahman ◽  
Mohammad Mahfuzul Islam
Keyword(s):  
Neural Network ◽  
Genetic Algorithm ◽  
Weight Matrix ◽  
Design Parameters ◽  
Close Relative ◽  
Convergence Criterion ◽  
Hull Form ◽  
Form Design ◽  
Hull Form Design ◽  
Improved Design

Abstract This paper aims at developing a fully automated hull form design technique employing an Neural Network and Genetic Algorithm methods resulting in accelerated convergence. For generating an input data that will be, by and large, a close relative of the desired hull, a linear relation has been assumed between the half breadth of different sections and principal dimensions (length, breadth, draft or (displacement)1/3) of a particular type of vessel. Compared to starting with a random value of the input, this technique resulted in faster convergence. The weight matrix for each of these parameters is produced from data obtained from the population. The half-breadth table for a new vessel can be obtained by multiplying the weight matrix with corresponding parameter. However, the half-breadth table obtained in such way may not provide the required displacement and speed of the vessel. Therefore, some readjustments of some of the principal dimensions are required. Neural Networks (Wasserman, 1989) has been used to find the required values of such improved design parameters (principal dimensions). The final design process consists of searching for the exact solution by examining several generations generated by the GA (Goldberg, 1989). The convergence criterion is the summed offset error, which is to be within the envelope defined by the tolerances. Since GA doesn’t guarantee fairness of the surface of the hull form, B-spline curve fitting method is used to obtain a fair hull. Thus, the hull form generated through this process is fully automated, accurate and having fair surface. The technique is also found to be an efficient one.

An Improved Design Method of the MEMS-Based Folded-Beam Micromirror

2014 ◽  
Vol 529 ◽  
pp. 135-138
Author(s):  
Yan Mei Li ◽  
Qing Hua Chen ◽  
Ying Jun Chen ◽  
Wen Gang Wu
Keyword(s):  
Genetic Algorithm ◽  
Optimization Algorithm ◽  
Design Method ◽  
Search Algorithms ◽  
Improved Design

In this paper, the folded-beam torsion MEMS mirror that meets a set of specified constraints was developed. An optimization algorithm that we newly adopted in the RCS(restricted competition selection) GA(genetic algorithm) could overcome some difficulties in single-search algorithms. Moreover, by the proposed method, the designer’s experience, and view and judgment could be reflected effectively.

scholarly journals Implementation of GA with Position Based Crossover-PX Technique for Size Optimization of BDD Mapped Adder Circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 4215-4218
Keyword(s):  
Genetic Algorithm ◽  
Digital Circuits ◽  
Full Adder ◽  
System Optimization ◽  
Size Optimization ◽  
Variable Order ◽  
Decision Diagrams ◽  
Order Method ◽  
Binary Decision ◽  
Solution Formation

Binary Decision Diagrams or BDD are data structure used to represent single and multi-output digital circuits. BDD mapped adder circuits are used to represent different adder functions in a digital system. Optimization of adder circuits are done by optimizing the corresponding BDDs. In this work the optimization of BDD Mapped adder circuits are proposed by using genetic algorithm with position-based crossover-PX technique. The main feature of position-based crossover technique is that it is suitable for order-based solution formation. We compared our result with other existing variable order method available in BDD manipulation tool BuDDy-2.4. The result is obtained for Full Adder circuits of 1 to 8-bit size. Experimental results show the improvement of the proposed work over other techniques. The result is quite significant for large circuits i.e. full adder circuit having larger bit size.

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