A completely integrated single-chip phase-locked loop with a 15 GHz VCO using 0.2 μm E-/D-HEMT-technology

2002 ◽  
Author(s):  
P. Leber ◽  
W. Baumberger ◽  
M. Lang ◽  
M. Rieger-Motzer ◽  
W. Bronner ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Single Chip

Phase Locked Loop Integrated System

2010 ◽  
Vol 164 ◽  
pp. 221-226 ◽  
Author(s):  
J. Charlamov ◽  
R. Navickas
Keyword(s):  
Noise Analysis ◽  
Phase Locked Loop ◽  
Integrated System ◽  
Voltage Controlled Oscillator ◽  
Mems Devices ◽  
Single Chip ◽  
Fabrication Errors ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
A Charge

CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

Phase-Locked Loop Using Complex-Coefficient Filters for Grid-Connected Inverter

2013 ◽  
Vol 133 (4) ◽  
pp. 388-394 ◽  
Author(s):  
Akihiro Ohori ◽  
Nobuyuki Hattori ◽  
Tsuyoshi Funaki
Keyword(s):  
Phase Locked Loop ◽  
Complex Coefficient ◽  
Grid Connected Inverter

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS

2009 ◽  
Vol E92-C (6) ◽  
pp. 785-791 ◽  
Author(s):  
Hiroaki HOSHINO ◽  
Ryoichi TACHIBANA ◽  
Toshiya MITOMO ◽  
Naoko ONO ◽  
Yoshiaki YOSHIHARA ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
60 Ghz

Next Generation Laser Voltage Probing

2008 ◽  
Author(s):  
Yin S Ng ◽  
William Lo ◽  
Kenneth Wilsher
Keyword(s):  
Phase Modulation ◽  
Phase Locked Loop ◽  
Next Generation ◽  
Solid Immersion Lens ◽  
User Friendliness ◽  
New Developments ◽  
Polarization Difference ◽  
Previous Generation ◽  
Mode Locked Laser ◽  
Optical Laser

Abstract We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].

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