Interval Estimation of Relative Values in Residue Number System

2017 ◽  
Vol 27 (01) ◽  
pp. 1850004 ◽  
Author(s):  
Konstantin Isupov ◽  
Vladimir Knyazkov
Keyword(s):  
High Speed ◽  
Interval Estimation ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Limiting Factor ◽  
Small Integer ◽  
Magnitude Comparison ◽  
Mixed Radix Conversion ◽  
Residue Number

Residue number system (RNS), due to its carry-free nature, is popular in many applications of high-speed computer arithmetic, especially in digital signal processing and cryptography. However, the main limiting factor of RNS is a high complexity of such operations as magnitude comparison, sign determination and overflow detection. These operations have, for many years, been a major obstacle to more widespread use of parallel residue arithmetic. This paper presents a new efficient method to perform these operations, which is based on computation and analysis of the interval estimation for the relative value of an RNS number. The estimation, which is called the interval floating-point characteristic (IFC), is represented by two directed rounded bounds that are fixed-precision numbers. Generally, the time complexities of serial and parallel computations of IFC are linear and logarithmic functions of the size of the moduli set, respectively. The new method requires only small-integer and fixed-precision floating-point operations and focuses on arbitrary moduli sets with large dynamic ranges ([Formula: see text]). Experiments indicate that the performance of the proposed method is significantly higher than that of methods based on Mixed-Radix Conversion.

scholarly journals Reverse convertor design for the 4-moduli set {2ⁿ -1,2ⁿ, 2ⁿ +1,2²ⁿ+¹ -1} based on the mixed-radix conversion

2011 ◽  
Vol 24 (1) ◽  
pp. 89-103
Author(s):  
Negovan Stamenkovic ◽  
Bojan Jovanovic
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Hardware Architecture ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Mixed Radix Conversion ◽  
Residue Number

The residue number system (RNS) is an integer system capable of supporting high speed concurrent arithmetic. One of the most important consideration when designing RNS system is reverse conversion. The reverse converter for recently proposed for the four-moduli set {2? -1,2?, 2? +1,2??+? -1} is based on new Chinese remainder theorems II (New CRT-II) [6]. This paper presents an alternative architecture derived by Mixed-Radix conversion for this four-moduli set. Due to the using simple multiplicative inverses of the proposed moduli set, it can considerably reduce the complexity of the RNS to binary converter based on the Mixed-Radix conversion. The hardware architecture for the proposed converter is based on the adders and subtractors, without the needed ROM or multipliers.

scholarly journals High-Performance Computation in Residue Number System Using Floating-Point Arithmetic

Computation ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 9
Author(s):  
Konstantin Isupov
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Dynamic Range ◽  
Practical Interest ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Mixed Radix Conversion ◽  
Multiple Precision ◽  
Residue Number

Residue number system (RNS) is known for its parallel arithmetic and has been used in recent decades in various important applications, from digital signal processing and deep neural networks to cryptography and high-precision computation. However, comparison, sign identification, overflow detection, and division are still hard to implement in RNS. For such operations, most of the methods proposed in the literature only support small dynamic ranges (up to several tens of bits), so they are only suitable for low-precision applications. We recently proposed a method that supports arbitrary moduli sets with cryptographically sized dynamic ranges, up to several thousands of bits. The practical interest of our method compared to existing methods is that it relies only on very fast standard floating-point operations, so it is suitable for multiple-precision applications and can be efficiently implemented on many general-purpose platforms that support IEEE 754 arithmetic. In this paper, we make further improvements to this method and demonstrate that it can successfully be applied to implement efficient data-parallel primitives operating in the RNS domain, namely finding the maximum element of an array of RNS numbers on graphics processing units. Our experimental results on an NVIDIA RTX 2080 GPU show that for random residues and a 128-moduli set with 2048-bit dynamic range, the proposed implementation reduces the running time by a factor of 39 and the memory consumption by a factor of 13 compared to an implementation based on mixed-radix conversion.

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

2007 ◽  
Vol 16 (02) ◽  
pp. 267-286 ◽  
Author(s):  
ALEXANDER SKAVANTZOS ◽  
MOHAMMAD ABDALLAH ◽  
THANOS STOURAITIS
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
New Class ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Signal Processors

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

A high-speed division algorithm in residue number system using parity-checking technique

2004 ◽  
Vol 81 (6) ◽  
pp. 775-780 ◽  
Author(s):  
Jen-Ho Yang * ◽  
Chin-Chen Chang ◽  
Chien-Yuan Chen ‡
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Division Algorithm ◽  
Residue Number

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

2018 ◽  
Vol 57 (4) ◽  
pp. 361-375 ◽  
Author(s):  
J Jency Rubia ◽  
GA Sathish Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Large Scale ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Hardware Complexity ◽  
Logarithmic Number System ◽  
Logarithmic Number

The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

Implementation of floating point MAC using Residue Number System

2014 ◽  
Author(s):  
Dhanabal R ◽  
Barathi V ◽  
Sarat Kumar Sahoo ◽  
Naamatheertham R Samhitha ◽  
Neethu Acha Cherian ◽  
...  
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Residue Number
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