Reduced Triple Modular redundancy for built-in self-repair in VLIW-processors

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

Download Full-text

A Novel Scheme for Fault Tolerant Computing

Journal of the Institute of Electronics and Computer ◽

10.33969/jiec.2021.31002 ◽

2021 ◽

Vol 3 (1) ◽

pp. 17-23

Author(s):

Pramode Ranjan Bhattacharjee ◽

Keyword(s):

Fault Tolerant ◽

Present Scheme ◽

Triple Modular Redundancy ◽

Test Input ◽

Digital Network ◽

Additional Control ◽

Majority Voter ◽

Modular Redundancy ◽

Primary Output

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

Download Full-text

Double cell upsets mitigation through triple modular redundancy

Microelectronics Journal ◽

10.1016/j.mejo.2019.104683 ◽

2020 ◽

Vol 96 ◽

pp. 104683

Author(s):

Yuanqing Li ◽

Anselm Breitenreiter ◽

Marko Andjelkovic ◽

Junchao Chen ◽

Milan Babic ◽

...

Keyword(s):

Triple Modular Redundancy ◽

Modular Redundancy

Download Full-text

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Electronics ◽

10.3390/electronics8030332 ◽

2019 ◽

Vol 8 (3) ◽

pp. 332 ◽

Cited By ~ 7

Author(s):

Tooba Arifeen ◽

Abdus Hassan ◽

Jeong-A Lee

Keyword(s):

Fault Tolerant ◽

Triple Modular Redundancy ◽

Area Overhead ◽

Final Output ◽

Working Principle ◽

Fault Masking ◽

Internal Faults ◽

Modular Redundancy ◽

Power Delay Product

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

Download Full-text

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Applied Sciences ◽

10.3390/app9245400 ◽

2019 ◽

Vol 9 (24) ◽

pp. 5400 ◽

Cited By ~ 2

Author(s):

Padmanabhan Balasubramanian ◽

Douglas L. Maskell ◽

Nikos E. Mastorakis

Keyword(s):

Oxide Semiconductor ◽

Normal Operation ◽

Synthesis Methods ◽

Correct Operation ◽

Triple Modular Redundancy ◽

Majority Voter ◽

Function Modules ◽

Function Module ◽

Modular Redundancy ◽

Design Style

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.

Download Full-text