Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

2014 ◽  
Vol 61 (4) ◽  
pp. 239-243 ◽  
Author(s):  
Kang-Sub Kwak ◽  
Oh-Kyong Kwon
Keyword(s):  
Clock And Data Recovery ◽  
Power Reduction ◽  
Reduction Technique ◽  
Data Recovery ◽  
Single Edge ◽  
Edge Tracking

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique

2010 ◽  
Author(s):  
Kunal Desai ◽  
Rajasekhar Nagulapalli ◽  
Vijay Krishna ◽  
Rajkumar Palwai ◽  
Pravin Kumar Venkatesan ◽  
...  
Keyword(s):  
High Speed ◽  
Clock And Data Recovery ◽  
Reduction Technique ◽  
Data Recovery

scholarly journals A low jitter clock and data recovery with a single edge sensing Bang-Bang PD

2014 ◽  
Vol 11 (7) ◽  
pp. 20140088-20140088
Author(s):  
Taek-Joon Ahn ◽  
Sang-Soon Im ◽  
Yong-Sung Ahn ◽  
Jin-Ku Kang
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Single Edge ◽  
Low Jitter

scholarly journals A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  
Keyword(s):  
Data Streams ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Rf Power ◽  
Input Matching ◽  
Analog Front End ◽  
Frequency Mismatch ◽  
Free Running ◽  
Frequency Calibration ◽  
Total Sensitivity

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

Design of high-speed burst mode clock and data recovery IC for passive optical network

2005 ◽  
Author(s):  
Minhui Yan ◽  
Xiaobin Hong ◽  
Wei-Ping Huang ◽  
Jin Hong
Keyword(s):  
High Speed ◽  
Optical Network ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Passive Optical Network ◽  
Burst Mode

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

An all-digital semi-blind clock and data recovery system

2015 ◽  
Vol 46 (4) ◽  
pp. 273-284
Author(s):  
Mina Abdallah ◽  
Ahmed Eladawy ◽  
Ahmed Mohieldin
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Recovery System
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