scholarly journals Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550011
Author(s):  
Neeraja Jagadeesan ◽  
B. Saman ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. Jain
Keyword(s):  
Integrated Circuits ◽  
Quantum Well ◽  
Logic Gates ◽  
Digital Integrated Circuits ◽  
Short Channel ◽  
Flip Flop ◽  
Coupled Channels ◽  
Threshold Voltages ◽  
Sequential Logic ◽  
Quantum Well Devices

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

scholarly journals Vertical organic permeable dual-base transistors for logic circuits

2020 ◽  
Vol 11 (1) ◽  
Author(s):  
Erjuan Guo ◽  
Zhongbin Wu ◽  
Ghader Darbandy ◽  
Shen Xing ◽  
Shu-Jen Wang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vertical Channel ◽  
Logic Gates ◽  
Logic Circuits ◽  
Organic Transistors ◽  
Short Channel ◽  
Power Efficient ◽  
Threshold Voltages ◽  
Dual Gate ◽  
Dual Base

Abstract The main advantage of organic transistors with dual gates/bases is that the threshold voltages can be set as a function of the applied second gate/base bias, which is crucial for the application in logic gates and integrated circuits. However, incorporating a dual gate/base structure into an ultra-short channel vertical architecture represents a substantial challenge. Here, we realize a device concept of vertical organic permeable dual-base transistors, where the dual base electrodes can be used to tune the threshold voltages and change the on-currents. The detailed operation mechanisms are investigated by calibrated TCAD simulations. Finally, power-efficient logic circuits, e.g. inverter, NAND/AND computation functions are demonstrated with one single device operating at supply voltages of <2.0 V. We believe that this work offers a compact and technologically simple hardware platform with excellent application potential for vertical-channel organic transistors in complex logic circuits.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Efficient and Compact SR-flip Flop Optical Memory Based Photonic Crystals Platform

2021 ◽  
Author(s):  
Amr Hassan ◽  
Nihal F. F. Areed ◽  
Salah S. A. Obayya ◽  
Hamdi El Mikati
Keyword(s):  
Integrated Circuits ◽  
Optical Memory ◽  
Logic Gates ◽  
Power Input ◽  
Small Dimension ◽  
Square Lattice ◽  
Optical Logic ◽  
Flip Flop ◽  
Compact Size ◽  
Multiple Devices

Abstract The paper presents a different type of designing methods and operational improvements of the optical logic memory SR-flip flop (SR-FF). The proposed optical memory SR-FF is based on two optical NOR logic gates which use two-dimension (2D) photonic crystal (PhC) with a square lattice of silicon (Si) dielectric rods. The structure has a switching time in only a few Picoseconds with little power input and very little power loss. The proposed optical memory SR-FF has a small dimension 38x22 μm2 which makes it one of the best optimized and most practical structures to be used in all photonic integrated circuits (PICs). The ultra-compact size enables the possibility of multiple devices to be embedded in a single PIC chip.

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 136-141
Author(s):  
Xianghong Zhao ◽  
Jieyu Zhao ◽  
WeiMing Cai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
General Structure ◽  
Effective Solution ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Logic Functions ◽  
Structure And Design

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

scholarly journals Circuit Techniques in GaN Technology for High-Temperature Environments

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 42
Author(s):  
Ahmad Hassan ◽  
Jean-Paul Noël ◽  
Yvon Savaria ◽  
Mohamad Sawan
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
National Research Council ◽  
Logic Gates ◽  
Voltage Reference ◽  
Flip Flop ◽  
Wide Range ◽  
Circuit Techniques ◽  
First Time

As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltage reference circuits. The tested circuits are fabricated on a 4 mm × 4 mm chip to validate their functionality over a wide range of temperatures. The logic gates show functionality at HT over 400 °C, while the voltage reference circuits remain stable up to 550 °C.

Reliability of SiC Digital Telemetry Circuits on AlN Substrate

2014 ◽  
Vol 11 (1) ◽  
pp. 25-29 ◽  
Author(s):  
Reza Ghandi ◽  
Cheng-Po Chen ◽  
Liang Yin ◽  
Rich Saia ◽  
Tammy Johnson ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Random Vibration ◽  
Flip Chip ◽  
Logic Gates ◽  
Building Blocks ◽  
Mechanical Shock ◽  
Circuit Boards ◽  
Flip Flop ◽  
Gold Thin Film ◽  
Frequency Counter

In this work, two silicon carbide based integrated circuits (frequency counter and timing generator) have been designed, fabricated, and tested for functionality at 300°C and prove to operate continuously for more than 1,000 h. Further, the boards were subjected to random vibration at 20G RMS and also mechanical shock at 215G in a 300°C environment and remained operational after 8 h of vibration and 1,000 shocks. These boards are the building blocks of a digital telemetry module for the purpose of sensing and transmitting pressure measurements from a geothermal well at temperatures up to 300°C. The frequency counter consists of one 4-bit counter, one 4-bit shift register, and one buffer. The timing generator contains an 8-bit counter, a D-flip-flop, and some dedicated logic gates to generate timing pulses for the two channel frequency counter. These dice were flip-chip bonded to patterned gold thin-film aluminum nitride substrate circuit boards.

An All-Photonic Molecular Amplifier and Binary Flip-flop

2020 ◽  
Author(s):  
Thomas MacDonald ◽  
Timothy Schmidt ◽  
Jonathon Beves
Keyword(s):  
Numerical Modeling ◽  
Visible Light ◽  
Reaction Kinetics ◽  
Memory Storage ◽  
Chemical System ◽  
Initial Composition ◽  
Flip Flop ◽  
Sequential Logic ◽  
Behavior Based

A chemical system is proposed that is capable of amplifying small optical inputs into large changes in internal composition, based on a feedback interaction between switchable fluorescence and visible-light photoswitching. This system would demonstrate bifurcating reaction kinetics under irradiation and reach one of two stable photostationary states depending on the initial composition of the system. This behavior would allow the system to act as a chemical realization of the flip-flop circuit, the fundamental element in sequential logic and binary memory storage. We use detailed numerical modeling to demonstrate the feasibility of the proposed behavior based on known molecular phenomena, and comment on some of the conditions required to realize this system.

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