Sequential Test Decompressors with Fast Tester Bits Wide-Spreading

2017 ◽  
Vol 26 (08) ◽  
pp. 1740001
Author(s):  
Ondrej Novak ◽  
Jiri Jenicek ◽  
Martin Rozkovec
Keyword(s):  
Phase Shifter ◽  
Test Pattern ◽  
Linear Feedback ◽  
Linear Combinations ◽  
Test Access Mechanism ◽  
Test Application ◽  
Feedback Shift Register ◽  
Scan Chain ◽  
Test Vectors ◽  
Decoding Ability

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decoding ability as the number of free variables is limited by the test access mechanism bandwidth. We have found that even within this limitation, it is possible to improve the decodability by creating fast and wide-spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we proposed a decompressor combining a XOR network and a linear feedback shift register (LFSR)-like automaton; we place the XOR network on the LFSR inputs. We demonstrate that due to this arrangement, the combined decompressor can be used without any phase shifter or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

scholarly journals A Secure Architecture of Design for Testability Structures

2019 ◽  
Vol 8 (2) ◽  
pp. 2816-2820
Keyword(s):  
Design For Testability ◽  
Shift Register ◽  
Linear Feedback Shift Register ◽  
Linear Feedback ◽  
Test Vector ◽  
Area Overhead ◽  
Feedback Shift Register ◽  
Test Vectors ◽  
Reduction In Area ◽  
Secure Architecture

The structures of Scan-based Design for Testability are extremely susceptible towards unapproved access of the signals present inside the chip. This paper suggests a protected output based plan which averts the unapproved access without any compromise in the testability. A unique key for each test vector is provided in the proposed secure architecture. These inimitable keys are produced by a multi-polynomial linear feedback shift register (LFSR) in addition they are utilized as test vectors. The dimensions of the multi polynomial LFSR bit is saved bigger than the dimension of key so as to augment the level of security to the key. As the keys are concealed within the test vectors, there is reduction in area overhead. The amount of security is improved predominantly by changing the key for all test vectors, along with the location of the bit in the test vector by choosing a valid combination out of available test vector generated by multi polynomial LFSR.

scholarly journals Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 149-159
Author(s):  
Chien-In Henry Chen ◽  
Yingjie Zhou
Keyword(s):  
Test Pattern ◽  
Linear Feedback ◽  
Random Pattern ◽  
Multiple Sequence ◽  
Linear Feedback Shift Registers ◽  
Synthesis Procedure ◽  
Feedback Shift Registers ◽  
Self Test ◽  
Random Patterns ◽  
Test Vectors

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

scholarly journals Pseudorandom Testing – A Study of the Effect of the Generator Type

10.14311/686 ◽  
2005 ◽  
Vol 45 (2) ◽  
Author(s):  
P. Fišer ◽  
H. Kubátová
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Linear Feedback ◽  
Random Pattern ◽  
Generating Polynomial ◽  
Primitive Polynomials ◽  
Generator Type ◽  
Pattern Generators ◽  
Test Vectors

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results. 

Sign in / Sign up

Export Citation Format

Share Document