scholarly journals Condition of phase angle for a new VDGA-based multiphase variable phase shift oscillator from 0o to 90o

2020 ◽  
Vol 10 (4) ◽  
pp. 3801
Author(s):  
Kasim K. Abdalla
Keyword(s):  
Phase Angle ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Electronic Control ◽  
Variable Phase ◽  
Voltage Mode ◽  
Condition Of Oscillation ◽  
Simulation Results ◽  
First Time ◽  
Modern Building

A novel interesting type of variable phase angle voltage mode oscillator using modern building block has been presented in this paper. The new proposed oscillator configuration which uses four voltage differencing gain amplifier (VDGA) and two grounded capacitors can generate two sinusoidal signals that change out of phase by 0 to 90 degree. It has four floating and explicit voltage mode outputs where every two outputs have the same phase. The circuit is characterized by (i) the condition of phase angle of the oscillation (PO) (this concept is introduced for the first time in this paper) can be tuned electronically (ii) the gain of the floating outputs can be controlled independently (iii) it provides electronic control of condition of oscillation (CO) and independent control of frequency of oscillation (FO). The Total Harmonic Distortion (THD) of the output waveforms was obtained and the results were reasonability values (less than 4.5%). The non-ideal analysis and simulation results are investigated and confirmed the theoretical analysis based upon VDGAs implementable in 0.35μm CMOS technology. Simulation results include time response and frequency response outputs generated by using the PSPICE program.

NEW REALIZATIONS OF VOLTAGE-MODE QUADRATURE OSCILLATORS USING CURRENT DIFFERENCING BUFFERED AMPLIFIERS

2010 ◽  
Vol 19 (05) ◽  
pp. 1069-1076 ◽  
Author(s):  
ABHIRUP LAHIRI
Keyword(s):  
Point Of View ◽  
Passive Components ◽  
Voltage Mode ◽  
Sinusoidal Oscillators ◽  
Integration Point ◽  
Condition Of Oscillation ◽  
Simulation Results ◽  
Quadrature Oscillators

A number of sinusoidal oscillators using current differencing buffered amplifiers (CDBAs) have been reported in the literature. However, only three of them are canonic quadrature oscillators (i.e., requiring two capacitors). The aim of this letter is to present additional realizations of single/dual-resistance-controlled quadrature oscillators using CDBAs. Four voltage-mode quadrature oscillators are proposed, which provide the following advantageous features: (i) use of reduced and canonic component count, viz. two CDBAs, three/four resistors and two capacitors, (ii) all passive components are grounded or virtually grounded, which is favorable from integration point of view and (iii) independent and non-interactive resistor control of the condition of oscillation (CO) and the frequency of oscillation (FO). Simulation results verifying the workability of the proposed circuits have been included.

A NEW FOUR-CC-BASED CONFIGURATION FOR REALIZING A VOLTAGE-MODE BIQUAD FILTER

2002 ◽  
Vol 11 (03) ◽  
pp. 213-218 ◽  
Author(s):  
ABDHESH K. SINGH ◽  
RAJ SENANI
Keyword(s):  
Cmos Technology ◽  
Current Conveyors ◽  
Electronic Control ◽  
Pspice Simulations ◽  
Voltage Mode ◽  
Biquad Filter

A new voltage-mode (VM) biquad filter is presented, which employs four Current Conveyors (CC) along with five resistors and only two grounded capacitors, facilitates electronic control of filter parameters through grounded resistors (realizable by FETs/MOSFETs) and is suitable for IC implementation in bipolar or CMOS technology. The circuit offers several advantages over the four-CC-based VM biquads published earlier. The workability of the new circuit has been confirmed by PSPICE simulations.

A Novel CMOS CCCII with Wide Tunable Rx and Its Application

2018 ◽  
Vol 27 (13) ◽  
pp. 1850198 ◽  
Author(s):  
Cuirong Zhu ◽  
Chunhua Wang ◽  
Hua Chen ◽  
Xin Zhang ◽  
Jingru Sun ◽  
...  
Keyword(s):  
Tuning Range ◽  
Cmos Technology ◽  
Bias Current ◽  
Current Conveyor ◽  
Universal Filter ◽  
Intrinsic Resistance ◽  
External Bias ◽  
Simulation Results ◽  
First Time ◽  
Reconfigurable Structure

This paper introduces a novel CMOS second-generation current-controlled current conveyor (CCCII) that has a wide tunable intrinsic resistance ([Formula: see text]. The designed structure is achieved by the combination of one ordinary CCCII, one cross-coupled OTA and one active resistor. An inverse relationship between the intrinsic resistance and external bias current is created for the first time in CMOS CCCII design, which results in wide tuning range of [Formula: see text]. Performance of the proposed circuit is discussed by detailed analysis. The CMOS CCCII is simulated in TSMC 0.18[Formula: see text][Formula: see text]m RF CMOS technology. The simulation results confirm that the proposed CMOS CCCII achieves a wide tunable [Formula: see text] (from 197.4[Formula: see text][Formula: see text] to 27.23[Formula: see text]k[Formula: see text]) while maintaining favorable performance in bandwidth, transfer gain and linear range. In addition, a new reconfigurable structure, which can function as a universal filter or a quadrature oscillator via controlling an enabled switch, is given as an application example to validate the feasibility of the proposed CMOS CCCII.

Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation

2019 ◽  
Vol 29 (03) ◽  
pp. 2050038
Author(s):  
Mohammad Moradinezhad Maryan ◽  
Seyed Javad Azhari ◽  
Mehdi Ayat ◽  
Reza Rezaei Siahrood
Keyword(s):  
High Speed ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Saturation Region ◽  
Static Power ◽  
Linearity Error ◽  
Simulation Results ◽  
Compact Design ◽  
Four Quadrant

In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.

scholarly journals Voltage-Mode Four-Phase Sinusoidal Generator and Its Useful Extensions

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Sudhanshu Maheshwari
Keyword(s):  
High Frequency ◽  
Second Order ◽  
Voltage Mode ◽  
Active Elements ◽  
Generator Circuit ◽  
Condition Of Oscillation ◽  
Simulation Results ◽  
Parasitic Effects

This paper introduces a new voltage-mode second-order sinusoidal generator circuit with four active elements and six passive elements, including grounded capacitors. The frequency and condition of oscillation can be independently controlled. The effect of active element’s nonidealities and parasitic effects is also studied; the proposed topology is good in absorbing several parasitic elements involved with the active elements. The circuit is advantageous for generating high frequency signals which is demonstrated for 25 MHz outputs. Several circuit extensions are also given which makes the new proposal useful for real circuit adoption. The proposed theory is validated through simulation results.

New Voltage-Mode Sinusoidal Oscillators Using VDIBAs

2019 ◽  
Vol 29 (04) ◽  
pp. 2050052
Author(s):  
San-Fu Wang ◽  
Hua-Pin Chen
Keyword(s):  
Theoretical Analysis ◽  
Bias Current ◽  
Electronic Control ◽  
Active Components ◽  
Passive Components ◽  
Voltage Mode ◽  
Sinusoidal Oscillators ◽  
Oscillation Condition ◽  
Condition Of Oscillation ◽  
Minimum Number

This paper presents two new voltage-mode sinusoidal oscillators based on voltage differencing inverting buffered amplifier (VDIBA). The first proposed circuit exhibits independent and electronic control of oscillation condition by using the bias current of the VDIBA. The proposed configuration contains only single VDIBA, two grounded capacitors and two resistors, which are the least number of active components and the minimum number of passive components necessary for realizing voltage-mode oscillator topology. The second proposed circuit exhibits independent and electronic control on the condition of oscillation without affecting the oscillation frequency by adjusting the separate bias currents of the VDIBAs. The proposed configuration contains two VDIBAs, two grounded capacitors and one resistor, which can provide four quadrature voltage outputs simultaneously. Both proposed circuits enjoy only two grounded capacitors, which are suitable for monolithic integration. HSpice simulations and experimental results are included to confirm the theoretical analysis.

scholarly journals Simple Oscillator with Enlarged Tunability Range Based on ECCII and VGA Utilizing Commercially Available Analog Multiplier

2016 ◽  
Vol 16 (2) ◽  
pp. 35-41 ◽  
Author(s):  
Roman Sotner ◽  
Jan Jerabek ◽  
Norbert Herencsar ◽  
Jiun-Wei Horng ◽  
Kamil Vrba ◽  
...  
Keyword(s):  
Feedback Loop ◽  
Current Mode ◽  
Basic Structure ◽  
Electronic Control ◽  
Analog Multiplier ◽  
Voltage Mode ◽  
Voltage Amplifier ◽  
Circuit Structure ◽  
Condition Of Oscillation ◽  
Electronically Controllable

Abstract This work presents an example of implementation of electronically controllable features to an originally unsuitable circuit structure of oscillator. Basic structure does not allow any electronic control and has mutually dependent condition of oscillation (CO) and frequency of oscillation (FO) if only values of passive elements are considered as the only way of control. Utilization of electronically controllable current conveyor of second generation (ECCII) brings control of CO independent of FO. Additional application of voltage amplifier with variable gain in both polarities (voltage-mode multiplier) to feedback loop allows also important enlargement of the range of the independent FO control. Moreover, our proposal was tested and confirmed experimentally with commercially available active elements (“Diamond transistor”, current-mode multiplier, voltage-mode multiplier) in working range of tens of MHz.

scholarly journals A Bulk-Driven Quasi-Floating Gate Regulated Cascode Current Mirror and Its Application in Squarer Circuit

2022 ◽  
Author(s):  
bchir bchir ◽  
Mounira Bchir ◽  
Imen Aloui ◽  
Nejib Hassen
Keyword(s):  
Performance Improvement ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Floating Gate ◽  
Input Current ◽  
Current Mirror ◽  
Transfer Error ◽  
Simulation Results ◽  
Cascode Current Mirror

Abstract A regulated cascode current mirror (RGC) and its improved version with bulk driven quasi floating gate technique (BD-QFG) are presented in this paper. The proposed BD-QFG RGC current mirror (CM) is compared with the conventional (GD) RGC CM to show the performance improvement. The conventional and unconventional CM are implemented in Candace Virtuoso using 90 nm CMOS technology. For input current (Iin) varied from 0 to 200 μA and for 0.8 V supply voltage, the simulation results present that the proposed BD-QFG RGC CM has less variation in current transfer error (0.2%) as compared to the GD RGC CM (12%). The output voltage requirement for 200 µA input current is respectively 0.7 V and 0.17 V for the GD RGC CM and the BD-QFG RGC CM. The power consumption of the proposed circuit is 22.71 μW which is 0.15 μW higher than the GD RGC (22.56 μW). The total harmonic distortion (THD) of the proposed circuit is 0.4% which is 1.1% less than the conventional circuit (1.5%). All these improvements in the proposed BD-QFG RGC CM are attained at a cost of 0.05 GHz reduction in frequency (2.31 GHz). The minimum supply voltage of BD-QFG RGC CM and GD RGC CM is 0.4 V and

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

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