scholarly journals A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO

2017 ◽  
Vol 7 (1) ◽  
pp. 152 ◽  
Author(s):  
Nam-Jin Oh
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Single Stage ◽  
Voltage Controlled Oscillator ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Balanced Mixer

This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltage-controlled oscillator (VCO) exploiting a series <em>LC </em>(SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (<em>RC</em>) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW <em>dc</em> power from 1-V supply voltage.

scholarly journals A Single-Stage Quadrature LMVs

2018 ◽  
Vol 8 (1) ◽  
pp. 124
Author(s):  
Nam-Jin Oh
Keyword(s):  
Noise Figure ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Single Stage ◽  
Voltage Controlled Oscillator ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Offset Frequency ◽  
Voltage Conversion

This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.

A Low Power Low-Pass Fourth-Order Filter for WiMAX/LTE Receiver in CMOS 45nm Technology

2016 ◽  
Vol 26 (03) ◽  
pp. 1750048 ◽  
Author(s):  
Vida Orduee Niar ◽  
Gholamreza Zare Fatin
Keyword(s):  
Low Power ◽  
Fourth Order ◽  
Supply Voltage ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Power Filter ◽  
Order Filter ◽  
Source Follower ◽  
Low Pass ◽  
Circuit Technique

In this paper, a [Formula: see text]-[Formula: see text] low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22[Formula: see text]dBm, in-band noise density is 100[Formula: see text]nV/[Formula: see text]Hz and power consumption is 5.9[Formula: see text]mW. The supply voltage of the filter is equal to 1[Formula: see text]V.

scholarly journals Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2931
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Biomedical Sensors ◽  
Filter Synthesis ◽  
Cascade Method

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

scholarly journals Design and Implementation of High Performance PPSK demodulator in Biomedical Implant

2021 ◽  
Author(s):  
Hima Bindu Katikala ◽  
G.Ramana Murthy ◽  
Yatavakilla Amarendra Nath
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Data Transmission ◽  
High Performance ◽  
Large Scale ◽  
Analog Circuit ◽  
Supply Voltage ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass

Abstract The important challenge for the realization of hearing aids is small size, low cost, low power consumption and better performance, etc. Keeping these requirements in view this work concentrates on the VLSI (Very Large Scale Integrated) implementation of analog circuit that mimic the PPSK (Passive Phase Shift Keying) demodulator with low pass filter. This research deals with RF Cochlear implant circuits and their data transmission. A PPSK modulator is used for uplink data transmission in biomedical implants with simultaneous power, data transmission This paper deals about the implementation of PPSK demodulator with related circuits and low pass filter which are used in cochlear implants consumes low power and operates at 14MHz frequency. These circuits are designed using FINFET 20nm technology with 0.4v DC supply voltage. The performance of proposed design over the previous design is operating at low threshold voltage, reduces static leakage currents and often observed greater than 30 times of improvement in speed performance

scholarly journals A CMOS Programmable Fourth-Order Butterworth Active-RC Low-Pass Filter

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 204 ◽  
Author(s):  
Changchun Zhang ◽  
Long Shang ◽  
Yongkai Wang ◽  
Lu Tang
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Fully Differential ◽  
Low Pass ◽  
Low Sensitivity

This paper presents a low-pass filter (LPF) for an ultra-high frequency (UHF) radio frequency identification (RFID) reader transmitter in standard SMIC 0.18 μm CMOS technology. The active-RC topology and Butterworth approximation function are employed mainly for high linearity and high flatness respectively. Two cascaded fully-differential Tow-Thomas biquads are chosen for low sensitivity to process errors and strong resistance to the imperfection of the involved two-stage fully-differential operational amplifiers. Besides, the LPF is programmable in order to adapt to the multiple data rate standards. Measurement results show that the LPF has the programmable bandwidths of 605/870/1020/1330/1530/2150 kHz, the optimum input 1dB compression point of −7.81 dBm, and the attenuation of 50 dB at 10 times cutoff frequency, with the overall power consumption of 12.6 mW from a single supply voltage of 1.8 V. The silicon area of the LPF core is 0.17 mm2.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

scholarly journals Design and Implementation of Low Noise Amplifier At 60ghz using Current Mirror Feedback

2019 ◽  
Vol 8 (9S3) ◽  
pp. 249-254
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Single Stage ◽  
Common Source ◽  
Small Signal ◽  
Total Size ◽  
Noise Amplifier

This discourse used 45nm CMOS technology to design a Low noise amplifier for a Noise figure < 2dB and gain greater than 13dB at the 60GHz unlicensed band of frequency. A single stage, primary cascode LNA is modeled and its small signal model is analyzed. Common source structure is hired in the driver stage to escalate the output power with single stage contours. To enhance small signal gain, simple active transistor feedback and cascode feedback configurations are designed and appended to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is deliberated to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The measurement results indicated that the input match and the output gain at 60GHz achieves -8dB and 13dB respectively with the supply voltage of 900mV. The frequency response obtained is a narrow band response with 6GHz of bandwidth. The circuit is simulated by Cadence Virtuoso tool. The layout of the related circuit is drawn by means of the Virtuoso Layout editor with total size of 0.1699μm2.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE

2015 ◽  
pp. 171-174
Author(s):  
MOHAMMAD HADI DANESH ◽  
SASAN NIKSERESHT ◽  
MAHYAR DEHDAST
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Input Range ◽  
Low Supply Voltage

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

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