Subthreshold Characteristics and Interface State Density of a-Si:H TFT

1993 ◽  
Vol 297 ◽  
Author(s):  
Keiji Maeda ◽  
Hiroki Koyanagi ◽  
Toshihide Jinnai
Keyword(s):  
Gate Voltage ◽  
Room Temperature ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Subthreshold Region ◽  
Layer Width ◽  
Capacitance Measurements ◽  
Voltage Swing

Inverted-staggered a-Si:H TFT was prepared by successive PECVD of a- SiN1.7:H and a- Si:H layers. Drain current ID vs gate voltage VG characteristics of the TFT were investigated. The gate-voltage swing defined by S=dVG/d(log ID) in the subthreshold region was 1.4 V at room temperature. If the observed S value is attributed to the bulk gap state density, the space- charge layer width is estimated to be about 450 A. This value is too small compared with the a-Si:H layer width of about 3000 A in the TFT, which exhibits good performance. On the other hand, if the S value is attributed to the interface states, a state density of 1.5×l012 (cm2 eV)-1 is necessary. Nearly the same density, (l-2)xl012 (cm2 eV)-1, nearly independent of the energy level, was obtained in oura-SiN1.7:H/c-Si interface by capacitance measurements. Therefore, it is concluded that the interface states are the main origin of the subthreshold characteristics in our a-Si:H TFT.

scholarly journals Impedance and Interface Properties of Al/Methyl-Red/p-InP Solar Cell

2009 ◽  
Vol 2009 ◽  
pp. 1-7 ◽  
Author(s):  
Ömer Güllü
Keyword(s):  
Solar Cell ◽  
Barrier Height ◽  
Room Temperature ◽  
Short Circuit ◽  
Relaxation Times ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Open Circuit ◽  
Methyl Red

An Al/methyl-red/p-InP solar cell was fabricated via solution-processing method and was characterized by using current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) measurements at room temperature. From darkI-Vcharacteristics, the values of ideality factor and barrier height of the device were calculated as 1.11 eV and 2.02, respectively. It has been seen that the device exhibited a good photovoltaic behavior with a maximum open circuit voltageVocof 0.38 V and short-circuit currentIscof 2.8 nA under only 200 lx light intensity. The barrier height and acceptor carrier concentration values for the Al/methyl-red/p-InP devices were extracted as 1.27 eV and3.46×1017 cm-3from linear region of itsC-2-Vcharacteristics, respectively. The difference betweenΦb(I-V) andΦb(C-V) for Al/methyl-red/p-InP device was attributed the different nature of theI-VandC-Vmeasurements. Also, the energy distribution curves of the interface states and their time constants were obtained from the experimental conductance properties of the Al/methyl-red/p-InP structure at room temperature. The interface state densities and their relaxation times of the device have ranged from2.96×1012 cm-2eV-1and4.96×10-6s at (1.11-Ev) eV to5.19×1012 cm-2 eV-1and9.39×10-6s at (0.79-Ev) eV, respectively. It was seen that both the interface state density and the relaxation time of the interface states have decreased with bias voltage from experimental results.

Study of the impact of interface traps associated with SiNX passivation on AlGaN/GaN MIS-HEMTs

2022 ◽  
Author(s):  
Rijo Baby ◽  
Anirudh Venugopalrao ◽  
Hareesh Chandrasekar ◽  
Srinivasan Raghavan ◽  
Muralidharan Rangrajan ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Temperature Dependent ◽  
The Impact ◽  
Surface Conduction ◽  
Magnitude Improvement

Abstract In this work, we show that a bilayer SiNx passivation scheme which includes a high-temperature annealed SiNx as gate dielectric, significantly improves both ON and OFF state performance of AlGaN/GaN MISHEMTs. From devices with different SiNx passivation schemes, surface and bulk leakage paths were determined. Temperature-dependent MESA leakage studies showed that the surface conduction could be explained using a 2-D variable range hopping mechanism along with the mid-gap interface states at the GaN(cap)/ SiNx interface generated due to the Ga-Ga metal like bonding states. It was found that the high temperature annealed SiNx gate dielectric exhibited the lowest interface state density and a two-step C-V indicative of a superior quality SiNx/GaN interface as confirmed from conductance and capacitance measurements. High-temperature annealing helps in the formation of Ga-N bonding states, thus reducing the shallow metal-like interface states. MISHEMT measurements showed a significant reduction in gate leakage and a 4-orders of magnitude improvement in the ON/OFF ratio while increasing the saturation drain current (IDS) by a factor of 2. Besides, MISHEMTs with 2-step SiNx passivation exhibited a relatively flat transconductance profile, indicative of lower interface states density. The dynamic Ron with gate and drain stressing measurements also showed about 3x improvements in devices with bilayer SiNx passivation.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

Low- and High-Frequency C–V Characteristics of Au/n-GaN/n-GaAs

2018 ◽  
Vol 18 (06) ◽  
pp. 1850039
Author(s):  
Abderrezzaq Ziane ◽  
Mohamed Amrani ◽  
Abdelaziz Rabehi ◽  
Zineb Benamara
Keyword(s):  
Schottky Diode ◽  
High Frequency ◽  
High Vacuum ◽  
Low Frequency ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Ultra High Vacuum ◽  
Active Nitrogen ◽  
Capacitance Voltage

Au/GaN/GaAs Schottky diode created by the nitridation of n-GaAs substrate which was exposed to a flow of active nitrogen created by a discharge source with high voltage in ultra-high vacuum with two different thicknesses of GaN layers (0.7[Formula: see text]nm and 2.2[Formula: see text]nm), the I–V and capacitance–voltage (C–V) characteristics of the Au/n-GaN/n-GaAs structures were studied for low- and high-frequency at room temperature. The measurements of I–V of the Au/n-GaN/n-GaAs Schottky diode were found to be strongly dependent on bias voltage and nitridation process. The electrical parameters are bound by the thickness of the GaN layer. The capacitance curves depict a behavior indicating the presence of interface state density, especially in the low frequency. The interface states density was calculated using the high- and low-frequency capacitance curves and it has been shown that the interface states density decreases with increasing of nitridation of the GaAs.

High Temperature off Current in a-Si TFTS - Effect of Process and Structure

1991 ◽  
Vol 219 ◽  
Author(s):  
George E. Possin
Keyword(s):  
Room Temperature ◽  
Liquid Crystal Displays ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Hole Injection ◽  
Electron Conduction ◽  
Active Matrix ◽  
Silicon Thickness ◽  
Matrix Liquid

ABSTRACTThe OFF current in a-Si TFTs is an important parameter, especially for applications such as active matrix liquid crystal displays. In some demanding applications operation at 70°C or higher is required. This paper reports studies of the OFF current limiting mechanisms at room temperature and above. It is shown that the limiting mechanisms are hole injection from the drain junction at room temperature and electron conduction at higher temperatures. The importance of silicon thickness and interface state density at the passivation interface is stressed.

Fabrication and Characterization of 4H-SiC MOSFET with MOCVD-Grown Al2O3 Gate Insulator

2007 ◽  
Vol 556-557 ◽  
pp. 787-790 ◽  
Author(s):  
Shiro Hino ◽  
Tomohiro Hatayama ◽  
Naruhisa Miura ◽  
Tatsuo Oomori ◽  
Eisuke Tokumitsu
Keyword(s):  
Photoelectron Spectroscopy ◽  
Chemical Vapor ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Organic Chemical ◽  
Mos Capacitors ◽  
Significant Difference ◽  
Metal Organic

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

Electronic Properties of Thermally Oxidized Single-Domain 3C-SiC/6H-SiC Grown by Vapour-Liquid-Solid Mechanism

2007 ◽  
Vol 556-557 ◽  
pp. 505-508
Author(s):  
Kin Kiong Lee ◽  
Gerhard Pensl ◽  
Maher Soueidan ◽  
Gabriel Ferro
Keyword(s):  
Electronic Properties ◽  
Interface State ◽  
Average Concentration ◽  
State Density ◽  
Single Domain ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Capacitance Measurements ◽  
Sic Film ◽  
Sic Films

This paper studies the electronic properties of MOS capacitors fabricated on double positioning boundary free 3C-SiC/6H-SiC where the 3C-SiC films were grown using the Vapour- Liquid-Solid mechanism. The temperature- and frequency-dependent electrical properties of SiO2/3C-SiC/6H-SiC structures have been studied. Capacitance measurements indicate that the single-domain 3C-SiC film is doped near the surface with an average concentration of 8.3 × 1016 cm-3. The measured interface state density near the conduction band edge of 3C-SiC is below 1011cm-2⋅eV-1 and increases towards mid-gap as obtained from conductance and capacitance measurements. Our results are consistent with the assumption that the interfaces of SiO2/ n-type SiC consist of two different kinds of interface traps – the carbon clusters located at the interface and the intrinsic defects located within the oxide layer.

Electrical Properties of Au/Bi4-xLaxTi3O12 Thin Film/Si Structures and Reduction of Interface States

2005 ◽  
Vol 902 ◽  
Author(s):  
Atsushi Kohno ◽  
Hiroyuki Tomari
Keyword(s):  
Interfacial Layer ◽  
Sol Gel ◽  
Frequency Dispersion ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Flat Band ◽  
Silicon Substrates ◽  
Ft Ir ◽  
The Ideal

AbstractSub-100nm-Thick Polycrystalline Bi4-xLaxTi3O12 (BLT) thin films have been formed on silicon substrates by sol-gel and spin-coating techniques. The analysis of X-ray reflectivity for the BLT/Si structure showed that the BLT film density was slightly lower than the ideal value and the interfacial layer was formed. By Fourier transform infrared spectroscopy (FT-IR) it is confirmed that the formation of the interfacial layer was due to oxidation of Si. Clockwise hysteresis was observed in capacitance-voltage (C-V) characteristics for Au/BLT/p-Si structures at a frequency range between 1 MHz – 1 kHz. The frequency dispersion of the C-V curve was caused by a large amount of interface states at BLT/Si interface. As the film was crystallized at 550°C for 2 h the maximum interface state density was ∼3.4×1011 cm-2ev-1 at 1 kHz. Also, the negative gate-voltage shift of the C-V curve from the ideal curve and the gate-bias dependence of the flat-band voltage were observed, resulting in the presence of undesirable positive charges in the film and the electron injection to the traps near the BLT/Si interface. By post-annealing of the device at 400 °C in oxygen atmosphere the interface states (fast sates) were successfully reduced to a third of the initial value and also the positive charges were significantly diminished.

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