Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond

2002 ◽  
Vol 717 ◽  
Author(s):  
John O. Borland
Keyword(s):  
Low Temperature ◽  
Solubility Limit ◽  
Gate Stack ◽  
Solid Solubility Limit ◽  
Shallow Junction ◽  
Technology Node ◽  
Dopant Level ◽  
High K ◽  
Junction Formation ◽  
Low Power Cmos

AbstractLow temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Optimization of Fluorine Co-implantation for PMOS Source and Drain Extension Formation for 65nm Technology Node

2004 ◽  
Vol 810 ◽  
Author(s):  
H. Graoui ◽  
M. Hilkene ◽  
B. McComb ◽  
M. Castle ◽  
S. Felch ◽  
...  
Keyword(s):  
Solubility Limit ◽  
Junction Depth ◽  
Solid Solubility Limit ◽  
Enhanced Diffusion ◽  
Technology Node ◽  
Energy Needs ◽  
Junction Formation ◽  
Boron Implantation ◽  
The Right ◽  
Spike Annealing

ABSTRACTThe main challenges for PMOS ultra shallow junction formation remain the transient enhanced diffusion (TED) and the solid solubility limit of boron in silicon. It has been demonstrated that low energy boron implantation and spike annealing are key in meeting the 90 nm technology node ITRS requirements. To meet the 65 nm technology requirements many studies have used fluorine co-implantation with boron and Si+ or Ge+ pre-amorphization (PAI) and spike annealing. Although using BF+2 can be attractive for its high throughput, self-amorphization and the presence of fluorine, many studies have shown that for the fluorine to successfully reduce TED its energy needs to be well optimized with respect to the boron's, therefore BF+2 does not present the right fluorine/boron energy ratio for the optimum junction formation. In this work we optimize the fluorine energy when a deep or shallow PAI is used. We also demonstrate that the fluorine dose needs to be carefully optimized otherwise a reverse effect can be observed. We will also show that the optimized junction depends less on the Ge+ energies between 2 keV and 20 keV and when HF etch is implemented after Ge+ PAI, improvements in both the junction depth and the sheet resistance are observed.

Low temperature shallow junction formation using vacuum ultraviolet photons during rapid thermal processing

1997 ◽  
Vol 70 (13) ◽  
pp. 1700-1702 ◽  
Author(s):  
R. Singh ◽  
K. C. Cherukuri ◽  
L. Vedula ◽  
A. Rohatgi ◽  
S. Narayanan
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Vacuum Ultraviolet ◽  
Rapid Thermal Processing ◽  
Shallow Junction ◽  
Junction Formation ◽  
Ultraviolet Photons

Vacancy Enhanced Boron Activation during Room Temperature Implantation and Low Temperature Annealing

2000 ◽  
Vol 610 ◽  
Author(s):  
Jian-Yue Jina ◽  
Irene Rusakova ◽  
Qinmian Li ◽  
Jiarui Liu ◽  
Wei-Kan Chu
Keyword(s):  
Low Temperature ◽  
Sheet Resistance ◽  
Room Temperature ◽  
Activation Barrier ◽  
Promising Method ◽  
Activation Mechanism ◽  
Rich Region ◽  
Shallow Junction ◽  
Low Temperature Annealing ◽  
Junction Formation

AbstractLow temperature annealing combined with pre-damage (or preamorphization) implantation is a very promising method to overcome the activation barrier in ultra-shallow junction formation. We have made a 32 nm p+/n junction with sheet resistance of 290 /sq. using 20 keV 4×1014 Ω/cm2 Si followed by 2 keV 1×1015 at./cm2 B implantation and 10 minutes 550 °C annealing. This paper studies the boron activation mechanism during low temperature annealing. The result shows that placing B profile in the vacancyrich region has much better boron activation than placing B profile in interstitial-rich region or without pre-damage. It also shows that a significant portion of boron is in substitutional positions before annealing. The amount of substitutional boron is correlated to the amount of vacancies (damage) by the pre-damage Si implantation. The result supports our speculation that vacancy enhances boron activation.

Understanding and Controlling Transient Enhanced Dopant Diffusion in Silicon

1994 ◽  
Vol 354 ◽  
Author(s):  
P.A. Stolk ◽  
H.-J. Gossmann ◽  
D.J. Eaglesham ◽  
D.C. Jacobson ◽  
H.S. Luftman ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Activation Energy ◽  
Solubility Limit ◽  
Solid Solubility Limit ◽  
Near Surface ◽  
Enhanced Diffusion ◽  
Defect Clusters ◽  
Transmission Electron ◽  
Junction Formation ◽  
B Doping

AbstractImplanted B and P dopants in Si exhibit transient enhanced diffusion (TED) during initial annealing which arises from the excess interstitials generated by the implant. In order to study the mechanisms of TED, we have used B doping marker layers in Si to probe the injection of interstitials from near-surface, non-amorphizing Si implants during annealing. The in-diffusion of interstitials is limited by trapping at impurities and has an activation energy of -3.5 eV. Substitutional C is the dominant trapping center with a binding energy of 2-2.5 eV. The high interstitial supersaturation adjacent to the implant damage drives substitutional B into metastable clusters at concentrations below the B solid solubility limit. Transmission electron microscopy shows that the interstitials driving TED are emitted from {311} defect clusters in the damage region at a rate which also exhibits an activation energy of 3.6 eV. The population of excess interstitials is strongly reduced by incorporating substitutional C in Si to levels of ∼1019/cm3 prior to ion implantation. This provides a promising method for suppressing TED, thus enabling shallow junction formation in future Si devices through dopant implantation.

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