Studies on a Failure Analysis Flow of Surface Contamination, Corrosion, and Underetch on Microchip Al Bondpads in Wafer Fabrication

2005 ◽  
Author(s):  
Hua Younan
Keyword(s):  
Failure Analysis ◽  
Galvanic Corrosion ◽  
Surface Contamination ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Corrosion Passivation

Abstract A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.

Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing

2000 ◽  
Author(s):  
Y. N. Hua ◽  
E. C. Low ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Failure Analysis ◽  
Feed Rate ◽  
Galvanic Corrosion ◽  
Experimental Results ◽  
Metal Corrosion ◽  
Wafer Fabrication ◽  
Al Alloy ◽  
Assembly Process ◽  
Water Problem ◽  
Sawing Process

Abstract In our previous paper [1], discolored bondpads due to galvanic corrosion were studied. The results showed that the galvanic corrosion occurred in 0.8 ìm wafer fabrication (fab) process with cold Al alloy (Al-Si, 0.8 wt%-Cu, 0.5 wt%) metallization. Galvanic corrosion is also known as a two-metal corrosion and it could be due to either wafer fab process or assembly process. Our initial suspicion was that it was due to a DI water problem during wafer sawing at assembly process. After that, we did further failure analysis and investigation work on galvanic corrosion of bondpads and further found that galvanic corrosion might be due to longer rinsing time of DI water during wafer sawing. The rinsing time of DI water is related to the cutting time of wafer sawing. Therefore, some experiments of wafer sawing process were done by using different sizes of wafer (1/8 of wafer, a quadrant of wafer and whole of wafer) and different sawing speed (feed-rate). The results showed that if the cutting time was longer than 25 minutes, galvanic corrosion occurred on bondpads. However, if the cutting time was shorter than 25 minutes, galvanic corrosion was eliminated. Based on the experimental results, it is concluded that in order to prevent galvanic corrosion of bondpads, it is necessary to select higher feed-rate during wafer sawing process at assembly houses. In this paper, we will report the details of failure analysis and simulation experimental results, including the solution to eliminate galvanic corrosion of bondpads during wafer sawing at assembly houses.

Studies on Fingerprints of EDX, FTIR, XPS and TOF-SIMS Techniques and Applications in Failure Analysis of Wafer Fabrication

2004 ◽  
Author(s):  
Hua Younan ◽  
Lo Keng Foo ◽  
N. Ramesh Rao ◽  
Z. Q. Mo
Keyword(s):  
Failure Analysis ◽  
Functional Group ◽  
Complex Compounds ◽  
Ftir Spectra ◽  
The Other ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Wafer Fab ◽  
Ftir Technique

Abstract In failure analysis of wafer fabrication it is difficult to identify possible sources of carbon-related contaminants as most of them are from polymers, organic and complex compounds. In this paper, the fingerprints of EDX, FTIR, XPS and TOFSIMS techniques will be introduced so as to identify sources of carbon-related contaminants. For example, Si peak (1.740 keV) can be used as a fingerprint of EDX technique to identify the ink-related contaminant from the other carbon-related contaminants. FTIR spectra of more than 10 possible materials from wafer fab and assembly processes are discussed, which may be used as the fingerprints of FTIR technique to identify carbon-related contaminants. The C=O functional group and the PDMS (PolyDimethylSiloxane) are recommended as the fingerprints of XPS and TOF-SIMS techniques to identify source of carbon-related contaminants, respectively. In this paper, some application cases will be also discussed.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Principal Component Analysis (PCA) of Surface Contamination by TOF-SIMS

2021 ◽  
Author(s):  
Kei Lin Sek ◽  
Pei Lin Lee ◽  
Khin Yin Pang ◽  
Younan Hua ◽  
Lei Zhu ◽  
...  
Keyword(s):  
Principal Component Analysis ◽  
Principal Component ◽  
Component Analysis ◽  
Surface Contamination ◽  
Tof Sims
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