scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

2017 ◽  
Vol 897 ◽  
pp. 529-532 ◽  
Author(s):  
Luigi di Benedetto ◽  
Gian Domenico Licciardo ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Alfredo Rubino
Keyword(s):  
Figure Of Merit ◽  
Gate Oxide ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Wide Range ◽  
Source Voltage ◽  
Effect Transistor

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

The influence of a mounting manner of power MOS transistors on characteristics of the Totem-Pole circuit with RLC load

2016 ◽  
Vol 33 (3) ◽  
pp. 176-180 ◽  
Author(s):  
Pawel Górecki ◽  
Krzysztof Górecki
Keyword(s):  
The Other ◽  
Oxide Semiconductor ◽  
Mos Transistors ◽  
Content Type ◽  
Mos Transistor ◽  
Self Heating ◽  
Cross Section Area ◽  
Section Area ◽  
Wide Range ◽  
State Resistance

Purpose The paper aims to consider the problem of the influence of mounting power metal-oxide semiconductor (MOS) transistors operating in the Totem–Pole circuit on energy losses in this circuit. Design/methodology/approach Using the computer simulation in SPICE software, the influence of such factors as on-state resistance of the channel of the MOS transistor, the self-heating phenomena in this transistor and resistance of wires connecting transistors with the other part of the circuit on characteristics of the considered circuit operating with resistor, inductor and capacitor (RLC) load is analyzed. The selected results of calculations are compared with the results of measurements. Findings On the basis of the obtained results of calculations, some recommendations concerning the manner of mounting the considered transistors, assuring a high value of watt-hour efficiency of the process of energy transfer to the load are formulated. Research limitations/implications The investigations were performed in the wide range of the frequency of the signal stimulating the considered circuit, but the results of calculations were presented for 2 selected values of this frequency only. Practical implications The considered analysis was performed for the circuit dedicated to power supplied of an elecrolyser. Originality/value Presented results of calculations prove that in some situations, the value of watt-hour efficiency of the considered circuit is determined by the length and the cross-section area of the applied wires bringing the signal to the connectors of the transistors and to load. On the other hand, self-heating phenomena in the power MOS transistors can lead to doubling power losses in these devices.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

2011 ◽  
Vol 679-680 ◽  
pp. 645-648 ◽  
Author(s):  
Motoki Kobayashi ◽  
Hidetsugu Uchida ◽  
Akiyuki Minami ◽  
Toyokazu Sakata ◽  
Romain Esteve ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
High Performance ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Metal Gates ◽  
Blocking Voltage ◽  
Gate Oxide Integrity

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

scholarly journals Tetragonal–Cubic Phase Transition and Low-Field Dielectric Properties of CH3NH3PbI3 Crystals

Materials ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4215
Author(s):  
Roxana E. Patru ◽  
Hamidreza Khassaf ◽  
Iuliana Pasuk ◽  
Mihaela Botea ◽  
Lucian Trupina ◽  
...  
Keyword(s):  
Dielectric Properties ◽  
Current Knowledge ◽  
Cubic Phase ◽  
Relaxation Processes ◽  
Temperature Dependent ◽  
Thermally Activated ◽  
Low Field ◽  
Conduction Mechanisms ◽  
Temperature Ranges ◽  
Nyquist Plots

The frequency and temperature dependence of dielectric properties of CH3NH3PbI3 (MAPI) crystals have been studied and analyzed in connection with temperature-dependent structural studies. The obtained results bring arguments for the existence of ferroelectricity and aim to complete the current knowledge on the thermally activated conduction mechanisms, in dark equilibrium and in the presence of a small external a.c. electric field. The study correlates the frequency-dispersive dielectric spectra with the conduction mechanisms and their relaxation processes, as well as with the different transport regimes indicated by the Nyquist plots. The different energy barriers revealed by the impedance spectroscopy highlight the dominant transport mechanisms in different frequency and temperature ranges, being associated with the bulk of the grains, their boundaries, and/or the electrodes’ interfaces.

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