scholarly journals Simple Scheme for the Implementation of Low Voltage Fully Differential Amplifiers without Output Common-Mode Feedback Network

2020 ◽  
Vol 10 (4) ◽  
pp. 34
Author(s):  
Mario Renteria-Pinon ◽  
Jaime Ramirez-Angulo ◽  
Alejandro Diaz-Sanchez
Keyword(s):  
Figure Of Merit ◽  
Low Voltage ◽  
Cmos Process ◽  
Large Signal ◽  
Simple Scheme ◽  
Common Mode ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Feedback Network ◽  
Strong Inversion

A simple scheme to implement class AB low-voltage fully differential amplifiers that do not require an output common-mode feedback network (CMFN) is introduced. It has a rail to rail output signal swing and high rejection of common-mode input signals. It operates in strong inversion with ±300 mV supplies in a 180 nm CMOS process. It uses an auxiliary amplifier that minimizes supply requirements by setting the op-amp input terminals very close to one of the rails and also serves as a common-mode feedback network to generate complementary output signals. The scheme is verified with simulation results of an amplifier that consumes 25 µW, has a gain-bandwidth product (GBW) of 16.1 MHz, slew rate (SR) of 8.4 V/µs, the small signal figure of merit (FOMSS) of 6.49 MHz*pF/µW, the large signal figure of merit (FOMLS) of 3.39 V/µs*pF/µW, and current efficiency (CE) of 2.03 in strong inversion, with a 10 pF load capacitance.

Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers

2016 ◽  
Vol 25 (10) ◽  
pp. 1650124 ◽  
Author(s):  
S. Rekha ◽  
T. Laxminidhi
Keyword(s):  
Power Supply ◽  
Continuous Time ◽  
Efficient Solution ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Power Efficient ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Simulation Results

Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5[Formula: see text]V in 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1[Formula: see text]fF to tens of femto farads.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

Testing fully differential amplifiers using common mode feedback circuit: A case study

2015 ◽  
Author(s):  
Isis D. Bender ◽  
Guilherme S. Cardoso ◽  
Arthur C. de Oliveira ◽  
Lucas C. Severo ◽  
Alessandro Girardi ◽  
...  
Keyword(s):  
Feedback Circuit ◽  
Common Mode ◽  
Differential Amplifiers ◽  
Fully Differential

HIGH-FREQUENCY LINEAR MULTIPLE-OUTPUT CMOS TRANSCONDUCTANCE AMPLIFIER FOR CURRENT-MODE FILTERS

2006 ◽  
Vol 15 (05) ◽  
pp. 701-717 ◽  
Author(s):  
HSIAO WEI SU ◽  
YICHUANG SUN
Keyword(s):  
High Frequency ◽  
Dynamic Range ◽  
Low Voltage ◽  
Filter Design ◽  
Current Mode ◽  
Cmos Process ◽  
Common Mode ◽  
Differential Input ◽  
Transconductance Amplifier ◽  
Linear Differential

A high-frequency highly linear tunable CMOS multiple-output operational transconductance amplifier (MO-OTA) for fully balanced current-mode OTA and capacitor (OTA-C) filters is presented. The MO-OTA is based on the cross-coupled pairs at the input and provides two pairs of differential outputs. A simple common-mode feedback (CMFB) circuit to stabilize the DC output levels of the MO-OTA is also proposed and two such CMFB circuits are used by the MO-OTA. The proposed MO-OTA is suitable for relatively low voltage (2.5 V) applications as its circuit has only two MOS transistors between the supply and ground rails. Simulated in a TSMC 0.25 μm CMOS process using PSpice, the MO-OTA has at least ± 0.3 V linear differential input signal swing with a single 2.5 V power supply and operates up to 1 GHz frequency. The MO-OTA has a THD less than -46 dB for a differential input voltage of 0.9 Vp-p at 10 MHz, dynamic range (DR) at THD = -46 dB is over 50 dB, and power consumption (with the common-mode feedback circuit) is below 8 mW for the whole tuning range. A fully balanced multiple loop feedback current-mode OTA-C filter example using the proposed MO-OTA is presented. This example also shows that the current-mode follow-the-leader-feedback (FLF) structure can achieve good performances for OTA-C filter design.

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