scholarly journals Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Sensors ◽  
2020 ◽  
Vol 20 (16) ◽  
pp. 4612 ◽  
Author(s):  
Danilo Monda ◽  
Gabriele Ciarpi ◽  
Sergio Saponara
Keyword(s):  
Supply Voltage ◽  
Process Variations ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Conditions ◽  
Ring Oscillator ◽  
Space Applications ◽  
Technology Scaling ◽  
Voltage Controlled Oscillators ◽  
Lc Tank

This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals Design and implementation of 4 bit binary weighted current steering DAC

2020 ◽  
Vol 10 (6) ◽  
pp. 5642
Author(s):  
Jayeshkumar J. Patel ◽  
Amisha P. Naik
Keyword(s):  
Supply Voltage ◽  
Biomedical Application ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Transmission Gate ◽  
Linearity Error ◽  
Current Steering Dac ◽  
Binary Weighted

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

scholarly journals Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

2021 ◽  
Vol 23 (11) ◽  
pp. 184-197
Author(s):  
Pawan Srivastava ◽  
◽  
Dr. Ram Chandra Singh Chauhan ◽  
Keyword(s):  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Process Variations ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Voltage Controlled Oscillator ◽  
Phase Frequency Detector ◽  
Power Efficient ◽  
Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER

2009 ◽  
Vol 18 (01) ◽  
pp. 199-208 ◽  
Author(s):  
JEONG BEOM KIM
Keyword(s):  
Supply Voltage ◽  
Current Mode ◽  
Full Adder ◽  
Cmos Technology ◽  
Cmos Circuits ◽  
Cmos Circuit ◽  
Circuit Performance ◽  
Quaternary Logic ◽  
Binary Logic ◽  
Multiple Valued Logic

This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm standard CMOS technology with the supply voltage 2.5 V.

scholarly journals 1.5-V CMOS Current Multiplier/Divider

2018 ◽  
Vol 8 (3) ◽  
pp. 1478 ◽  
Author(s):  
Jetsdaporn Satansup ◽  
Worapong Tangsrirat
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Total Power ◽  
Total Power Consumption ◽  
Linearity Error ◽  
Low Supply Voltage ◽  
Circuit Technique

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented.  It is based on the use of a compact current quadratic cell able to operate at low supply voltage.  The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V.  Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

scholarly journals Advantageous Sampling of Correlated Current Signals to Supress Fixed-Pattern Noise in CMOS Imagers

2017 ◽  
Vol 12 (1) ◽  
pp. 47-55
Author(s):  
R. A. Souza ◽  
L. G. M. Ventura ◽  
A. R. S. Martins ◽  
D. W. de Lima Monteiro ◽  
L. P. Salles
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Process Variations ◽  
Current Mode ◽  
Physical Parameters ◽  
Basic Operation ◽  
Silicon Area ◽  
Cmos Imagers ◽  
Pattern Noise ◽  
Fixed Pattern Noise

The Active Pixel Sensor (APS) has been a vastly used integrated circuit topology in CMOS imagers. Mismatch of physical parameters among pixels, caused by process variations, introduces Fixed-Pattern Noise (FPN) at the array output. Correlated Double Sampling (CDS) in voltage mode is a commonly used method to suppress the offset caused FPN. However, it increases the complexity as well as the demanded silicon area of either the pixel or the external circuitry, besides having its signal swing restricted by the supply voltage. An alternative CDS circuit operating in current mode to reduce FPN is presented in this paper. The correlated current signals are sampled and subtracted using a simpler circuitry, leading to a more efficient relation of FPN reduction for the required silicon area. Furthermore, this technique does not change the APS topology or basic operation cycle. A simulated and tested CDS alternative is presented, and a simulated further improved version is proposed. Simulation and experiments showed a 40% FPN reduction with the fabricated CDS, whereas the improved simulated version ensures 90% FPN reduction.

scholarly journals CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 193
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md. Rownak Hossain ◽  
Khairun Nisa’ Minhad ◽  
Fahmida Haque ◽  
Mohammad Shahriar Khan Hemel ◽  
...  
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Process Variations ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Oxide Semiconductor ◽  
Voltage Regulator ◽  
Stable Operation ◽  
Short Channel ◽  
Voltage Range

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

Statistical Simulations on Perceptron-Based Adders

2011 ◽  
pp. 1474-1481
Author(s):  
Snorre Aunet ◽  
Hans Kristian Otnes Berge
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Reducing Power ◽  
Process Variations ◽  
Full Adder ◽  
Cmos Technology ◽  
Subthreshold Cmos ◽  
Order Of Magnitude ◽  
Supply Voltages ◽  
Circuit Technique

In this article we compare a number of full-adder (1- bit addition) cells regarding minimum supply voltage and yield, when taking statistical simulations into account. According to the ITRS Roadmap two of the most important challenges for future nanoelectronics design are reducing power consumption and increasing manufacturability (ITRS, 2005). We use subthreshold CMOS, which is regarded by many as the most promising ultra low power circuit technique. It is also shown that a minimum redundancyfactor as low as 2 is sufficient to make circuits maintain full functionality under the presence of defects. This is, to our knowledge, the lowest redundancy reported for comparable circuits, and builds on a method suggested a few years ago (Aunet & Hartmann, 2003). A standard Full-Adder (FA) and an FA based on perceptrons exploiting the “mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating “open” faults, with gate-level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2 (Aunet & Otnes Berge, 2007). Two additional perceptrons do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations

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