scholarly journals Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs lifetime by Reliability Tests

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5627
Author(s):  
Fabio Principato ◽  
Giuseppe Allegra ◽  
Corrado Cappello ◽  
Olivier Crepel ◽  
Nicola Nicosia ◽  
...  
Keyword(s):  
High Temperature ◽  
Neutron Irradiation ◽  
Neutron Fluence ◽  
Electrical Characterization ◽  
Gate Oxide ◽  
Power Devices ◽  
Electrical Parameters ◽  
Power Mosfets ◽  
The Impact ◽  
Dc Characterization

High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 2× 1011 (n/cm2). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

2018 ◽  
Vol 33 (12) ◽  
pp. 10764-10773 ◽  
Author(s):  
Ujjwal Karki ◽  
Fang Zheng Peng
Keyword(s):  
Gate Oxide ◽  
Electrical Parameters ◽  
Power Mosfets ◽  
Oxide Degradation

Electrical Characterization of 1.2 kV-Class SiC MOSFET at High Temperature up to 380°C

2016 ◽  
Vol 858 ◽  
pp. 885-888 ◽  
Author(s):  
Yuichiro Nanen ◽  
Masatoshi Aketa ◽  
Yuki Nakano ◽  
Hirokazu Asahara ◽  
Takashi Nakamura
Keyword(s):  
High Temperature ◽  
Temperature Dependence ◽  
Electrical Characterization ◽  
Transfer Time ◽  
Static Characteristics ◽  
Power Mosfets ◽  
Turn On ◽  
Switching Losses ◽  
Gate Resistance

Dynamic and static characteristics of SiC power MOSFETs at high temperature up to 380°C were investigated. Investigated devices have exhibited a behavior as a normally-off MOSFET even at such high temperature as 380°C. Temperature dependence of the MOSFET characteristics are reported in this paper, such as threshold voltage (VTH), on-resistance, internal gate resistance, and turn-on and turn-off losses (EON, EOFF). EON decreases and EOFF increases with increased temperature. Temperature dependence of switching losses is affected by transfer time of VDS, which was mainly determined from VTH.

Impact of Channel Mobility Improvement Using Boron Diffusion on Different Power MOSFETs Voltage Classes

2017 ◽  
Vol 897 ◽  
pp. 537-540
Author(s):  
Victor Soler ◽  
Maria Cabello ◽  
Maxime Berthou ◽  
Josep Montserrat ◽  
José Rebollo ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Pin Diode ◽  
Boron Diffusion ◽  
Oxide Formation ◽  
Interface Quality ◽  
Channel Mobility ◽  
Power Mosfets ◽  
The Impact ◽  
Effective Channel ◽  
Drift Layer

SiC planar VDMOS of three voltages ratings (1.7kV, 3.3kV and 4.5kV) have been fabricated using a Boron diffusion process into the thermal gate oxide for improving the SiO2/SiC interface quality. Experimental results show a remarkable increase of the effective channel mobility which increases the device current capability, especially at room temperatures. At high temperatures, the impact of the Boron treatment is lower since the major contribution of the drift layer to the on-resistance. In addition, the intrinsic body diode characteristics approximate to that of an ideal PiN diode, and the blocking capability is not compromised by the use of Boron for the gate oxide formation.

The Reliability Prediction of HTR’s Graphite Component in Various Temperature and Neutron Dose Levels

2013 ◽  
Author(s):  
Xiang Fang ◽  
Haitao Wang ◽  
Xingtuan Yang ◽  
Suyuan Yu
Keyword(s):  
High Temperature ◽  
Neutron Irradiation ◽  
Three Dimensional ◽  
Reactor Core ◽  
Neutron Dose ◽  
Element Analysis ◽  
The Core ◽  
Three Dimensional Finite Element ◽  
Dose Levels ◽  
The Impact

In high temperature gas-cooled reactors (HTRs), graphite is used as the main structure material. The side reflecter of the reactor core is composed by a pile of graphite bricks. In real operational condition of the reactor, both high temperature and fast neutron irradiation have great effect on the behavior of graphite components. The non-uniform distribution of temperature and neutron dose cause obvious stress accumulation, which greatly affects the security and reliability of the graphite components. In addition, high temperature and neutron irradiation make the properties of graphite change in evidence, and the changes are not linear. Such changes must be considered and simulated in the calculation, in order to predict the stress concentration condition and the reliability of the graphite brick correctly. A FORTRAN code based on user subroutines of MSC.MARC is developed in INET in order to perform three-dimensional finite element analysis of irradiated behavior of the graphite components for the HTRs. In this paper, the stress level and failure probability of graphite components are calculated and obtained under different in-core temperatures and neutron dose levels of the core side of brick. 400°C, 500°C, 600°C and 700°C are selected as the core side temperature, while the range of neutron dose is 0 to 1022n cm-2 (EDN). Different constitutive laws are used in stress analysis procedure. The impact of different temperature and neutron dose levels are discussed.

Degradation of SiO2/SiC Interface Properties due to Mobile Ions Intrinsically Generated by High-Temperature Hydrogen Annealing

2014 ◽  
Vol 778-780 ◽  
pp. 541-544 ◽  
Author(s):  
Atthawut Chanthaphan ◽  
Takuji Hosoi ◽  
Yuki Nakano ◽  
Takashi Nakamura ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
High Temperature ◽  
Electrical Characterization ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Interface Properties ◽  
Mos Capacitors ◽  
State Densities ◽  
Mobile Ions ◽  
The Impact

The impact of mobile ions intrinsically generated in thermally grown SiO2by high-temperature forming gas annealing (FGA) on the SiO2/4H-SiC interface properties was studied by means of electrical characterization of SiC metal-oxide-semiconductor (MOS) capacitors. Unlike Si devices, mobile ions located at the interfaces were found to cause a remarkable stretch-out of capacitance-voltage (C-V) curve near the accumulation condition, and the degree of stretch-out was more pronounced with increasing probe frequency. This suggests that the interface states with a long emission time constant are formed near the conduction band edge due to the mobile ions. To clarify this unusual phenomenon, several characterization techniques to evaluate interface state densities (Dit), including Terman, conductance, and C-ψsmethods, were employed. The Ditvalues estimated for SiO2/SiC interfaces with mobile ions were a few times as large as those without mobile ions.

Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing

2008 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
P.K. Tan ◽  
Y.W. Goh ◽  
J.L. Cai ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electronic Devices ◽  
Random Access ◽  
Electrical Characterization ◽  
Electrical Parameters ◽  
Access Memory ◽  
Nanoscale Sram ◽  
Site Identification ◽  
The Impact

Abstract As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.

SiC Power Devices – An Overview

2004 ◽  
Vol 815 ◽  
Author(s):  
Anant Agarwal ◽  
Mrinal Das ◽  
Sumithra Krishnaswami ◽  
John Palmour ◽  
James Richmond ◽  
...  
Keyword(s):  
Schottky Diodes ◽  
Gate Oxide ◽  
Current Gain ◽  
Power Devices ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Power Mosfets ◽  
Voltage Instability ◽  
Igbt Modules ◽  
Near Future

ABSTRACTAn overview of SiC Power Devices is provided. Progress in 1200 V SiC Schottky diodes, 1200 V SiC BJTs, 10-20 kV SiC PiN diodes and 2 kV SiC Power MOSFETs will be described. SiC Schottky diodes have already been commercialized. The next step of inserting these diodes in Si IGBT modules is happening now. Emphasis is placed on the problems and issues at the SiC device/process interface which need to be urgently addressed such as the roughness created during the implant anneals, reliability of the gate oxide under positive and negative bias, low current gain of the BJTs, forward voltage instability in the pn junctions etc. Overcoming these issues in the near future will be critical to the successful commercialization of SiC devices.

Study of Geometrical Effects in Charge Pumping Current for Lateral SiC nMOSFETs Electrical Characterization

2015 ◽  
Vol 821-823 ◽  
pp. 717-720
Author(s):  
Matthieu Florentin ◽  
Joan Marc Rafi ◽  
Florian Chevalier ◽  
Victor Soler ◽  
Leszek Konczewicz ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Electrical Parameters ◽  
Charge Pumping ◽  
Geometrical Effects ◽  
A Charge ◽  
The Impact

In this work, a charge pumping characterization has been carried out on 4H-SiC nMOSFETs built with different SiC doping processes. Because charge pumping (CP) measurements on SiC are complex to implement, three different CP methods have been used for Ditcharacterization. The impact of geometrical and electrical parameters on each method is studied. Finally, it is detailed the full measurement flow chosen for a deeper and more accurate understanding of Ditelectrical characterization.

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

Sign in / Sign up

Export Citation Format

Share Document