scholarly journals FDTD Modeling with Passive Shielding for Crosstalk Reduction in Coupled RLC Interconnects

2019 ◽  
Vol 8 (3) ◽  
pp. 4965-4970
Keyword(s):  
Crosstalk Noise ◽  
Worst Case ◽  
Delay Reduction ◽  
Proposed Model ◽  
Rlc Interconnects ◽  
Crosstalk Reduction ◽  
Global Interconnects

This paper presents passive shielding technique for crosstalk noise and delay reduction in resistive driven RLC interconnect. FDTD technique is used for modeling proposed geometry. The worst case delay and noise induced due to crosstalk in passive shielded interconnects are compared with unshielded lines and is validated using HSPICE simulations for 32nm global interconnects. From the results it has been demonstrated that the proposed model results and HSPICE simulations differ by 8% and by using proposed geometry crosstalk noise and delay has come down by 90% and 52% when compared to unshielded line.

scholarly journals FDTD modeling for Crosstalk Reduction in Coupled RLC Interconnects with Active Shielding

2019 ◽  
Vol 8 (11) ◽  
pp. 1038-1042
Keyword(s):  
Crosstalk Noise ◽  
Delay Reduction ◽  
Proposed Model ◽  
Rlc Interconnects ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Active Shielding

This paper presents efficient geometry for crosstalk noise and delay reduction using Active shielding in RLC interconnects with resistive drivers .FDTD modeling has been used for proposed geometry and is validated by HSPICE simulations for 32nm global interconnects .From the results it has been verified that the proposed model results and HSPICE simulations differ by 5% . From the outcomes it has been confirmed that the proposed model outcomes and HSPICE outcomes differ by 5% and by using proposed geometry crosstalk noise and delay has come down by 73% and 60% when compared to unshielded line

Geometry Induced Crosstalk Reduction in CNT Interconnects for VLSI Circuits

2018 ◽  
Vol 24 (8) ◽  
pp. 5778-5784
Author(s):  
P. Uma Sathyakam ◽  
Paridhi Singh ◽  
Priyamanga Bhardwaj ◽  
P. S Mallick
Keyword(s):  
Carbon Nanotube ◽  
Transmission Line ◽  
Vlsi Circuits ◽  
Delay Reduction ◽  
Capacitively Coupled ◽  
Coupling Capacitance ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Transmission Line Models

This paper proposes novel triangular cross sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and hence, delay reduction in CNT bundle interconnects for VLSI circuits. We formulate the equivalent single conductor (ESC) transmission line models of the interconnects and show that the coupling capacitance of triangular bundle is 29% lesser than the traditionally used square bundles of carbon nanotube interconnects. We further simulate the proposed ESC models of capacitively coupled CNT bundle interconnects using Smart SPICE and find that the crosstalk induced delay of triangular interconnects is 30% lesser as compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs increase in the bundle. From these results, we suggest that triangle cross-sectioned CNT bundles are the most suitable candidates as global interconnects.

Geometry-Based Crosstalk Reduction in CNT Interconnects

2019 ◽  
Vol 29 (06) ◽  
pp. 2050094 ◽  
Author(s):  
P. Uma Sathyakam ◽  
P. S. Mallick ◽  
Paridhi Singh
Keyword(s):  
Carbon Nanotube ◽  
Transmission Line ◽  
Vlsi Circuits ◽  
Delay Reduction ◽  
Capacitively Coupled ◽  
Coupling Capacitance ◽  
Propagation Delays ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Transmission Line Models

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

Risk-Based Robust Bidding Strategies for EVs’ Aggregators in Day-ahead Markets with Uncertainty

2020 ◽  
Author(s):  
Ahmed Abdelmoaty ◽  
Wessam Mesbah ◽  
Mohammad A. M. Abdel-Aal ◽  
Ali T. Alawami
Keyword(s):  
Robust Optimization ◽  
Electricity Market ◽  
Real Life ◽  
Optimization Approach ◽  
Case Scenario ◽  
Worst Case ◽  
Bidding Strategies ◽  
Wind Generators ◽  
Proposed Model ◽  
Optimal Bidding

In the recent electricity market framework, the profit of the generation companies depends on the decision of the operator on the schedule of its units, the energy price, and the optimal bidding strategies. Due to the expanded integration of uncertain renewable generators which is highly intermittent such as wind plants, the coordination with other facilities to mitigate the risks of imbalances is mandatory. Accordingly, coordination of wind generators with the evolutionary Electric Vehicles (EVs) is expected to boost the performance of the grid. In this paper, we propose a robust optimization approach for the coordination between the wind-thermal generators and the EVs in a virtual<br>power plant (VPP) environment. The objective of maximizing the profit of the VPP Operator (VPPO) is studied. The optimal bidding strategy of the VPPO in the day-ahead market under uncertainties of wind power, energy<br>prices, imbalance prices, and demand is obtained for the worst case scenario. A case study is conducted to assess the e?effectiveness of the proposed model in terms of the VPPO's profit. A comparison between the proposed model and the scenario-based optimization was introduced. Our results confirmed that, although the conservative behavior of the worst-case robust optimization model, it helps the decision maker from the fluctuations of the uncertain parameters involved in the production and bidding processes. In addition, robust optimization is a more tractable problem and does not suffer from<br>the high computation burden associated with scenario-based stochastic programming. This makes it more practical for real-life scenarios.<br>

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

2013 ◽  
Vol 21 (10) ◽  
pp. 1823-1836 ◽  
Author(s):  
Yiyuan Xie ◽  
Mahdi Nikdast ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Networks ◽  
Case Analysis ◽  
Worst Case Analysis ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip

ACCURATE ANALYSIS OF GLOBAL INTERCONNECTS IN NANO-FPGAs

NANO ◽  
2009 ◽  
Vol 04 (03) ◽  
pp. 171-176 ◽  
Author(s):  
DAVOOD FATHI ◽  
BEHJAT FOROUZANDEH
Keyword(s):  
Propagation Delay ◽  
Modeling Method ◽  
Accurate Analysis ◽  
Proposed Model ◽  
Simulation Results ◽  
The Difference ◽  
A New Technique ◽  
Global Interconnects ◽  
Technology Nodes ◽  
Model Technique

This paper introduces a new technique for analyzing the behavior of global interconnects in FPGAs, for nanoscale technologies. Using this new enhanced modeling method, new enhanced accurate expressions for calculating the propagation delay of global interconnects in nano-FPGAs have been derived. In order to verify the proposed model, we have performed the delay simulations in 45 nm, 65 nm, 90 nm, and 130 nm technology nodes, with our modeling method and the conventional Pi-model technique. Then, the results obtained from these two methods have been compared with HSPICE simulation results. The obtained results show a better match in the propagation delay computations for global interconnects between our proposed model and HSPICE simulations, with respect to the conventional techniques such as Pi-model. According to the obtained results, the difference between our model and HSPICE simulations in the mentioned technology nodes is (0.29–22.92)%, whereas this difference is (11.13–38.29)% for another model.

scholarly journals Delay Bound Optimization in NoC Using a Discrete Firefly Algorithm

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1507
Author(s):  
Gaoming Du ◽  
Chao Tian ◽  
Zhenmin Li ◽  
Duoli Zhang ◽  
Chuan Zhang ◽  
...  
Keyword(s):  
Firefly Algorithm ◽  
Optimization Method ◽  
Video Object ◽  
Worst Case ◽  
Delay Bound ◽  
Proposed Model ◽  
Discrete Firefly Algorithm ◽  
Firefly Optimization ◽  
On Chip ◽  
Bound Optimization

The delay bound in system on chips (SoC) represents the worst-case traverse time of on-chip communication. In network on chip (NoC)-based SoC, optimizing the delay bound is challenging due to two aspects: (1) the delay bound is hard to obtain by traditional methods such as simulation; (2) the delay bound changes with the different application mappings. In this paper, we propose a delay bound optimization method using discrete firefly optimization algorithms (DBFA). First, we present a formal analytical delay bound model based on network calculus for both unipath and multipath routing in NoCs. We then set every flow in the application as the target flow and calculate the delay bound using the proposed model. Finally, we adopt firefly algorithm (FA) as the optimization method for minimizing the delay bound. We used industry patterns (video object plane decoder (VOPD), multiwindow display (MWD), etc.) to verify the effectiveness of delay bound optimization method. Experiments show that the proposed method is both effective and reliable, with a maximum optimization of 42.86%.

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