Improved Performance of 4H-SiC MESFET with Stepped-Channel

A novel 4H-SiC MESFET with stepped-channel (stepped-spacer) structure is proposed for the first time and analyzed by 2D numerical simulation. Based on the stepped buried oxide structure of SOI which can produce additional electrical Electric field peaks, much more advantages can be obtained through a stepped-channel structure compared to that of the field terminal technology, such as an obvious increase of the breakdown voltage which is equal to the electric field to the path integral, and the lower capacitances lead to a higher cut-off frequency. The simulation results show that a 100% higher saturated drain current and a 153% larger breakdown voltage can be obtained utilizing the stepped-channel structure MESFET than those of the conventional counterpart.

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60 GHz Double Deck T-Gate AlN/GaN/AlGaN HEMT for V-Band Satellites

10.21203/rs.3.rs-627623/v1 ◽

2021 ◽

Author(s):

A.S. Augustine Fletcher ◽

D Nirmal ◽

J Ajayan ◽

L Arivazhagan ◽

Husna Hamza K ◽

...

Keyword(s):

Electric Field ◽

Breakdown Voltage ◽

Figure Of Merit ◽

Drain Current ◽

60 Ghz ◽

Mechanical Reliability ◽

Gan Hemt ◽

V Band ◽

Silicon Carbide Substrate ◽

Gate Edge

Abstract The influence of double deck T-gate on LG=0.2 μm AlN/GaN/AlGaN HEMT is analysed in this paper. The T-gate supported with Silicon Nitride provides a tremendous mechanical reliability. It drops off the crest electric-field at gate edges and postponing the breakdown voltage of a device. A 0.2-μm double deck T-gate HEMT on Silicon Carbide substrate offer fMAX of 107 Giga Hertz, fT of 60 Giga Hertz and the breakdown voltage of 136 Volts. Furthermore, it produces the maximum-transconductance and drain-current of 0.187 Siemens/mm and 0.41 Ampere/mm respectively. In addition, the lateral electric-field noticed at gate-edge shows 2.1×106 Volts/cm. Besides, the double deck T-gate AlN/GaN HEMT achieves a 45 % increment in breakdown voltage compared to traditional GaN-HEMT device. Moreover, it reveals a remarkable Johnson figure-of-merit of 7.9 Tera Hertz Volt. Therefore, the double deck T-gate on AlN/GaN/AlGaN HEMT is the superlative device for 60 GHz V-band satellite application.

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An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.717.158 ◽

2013 ◽

Vol 717 ◽

pp. 158-163

Author(s):

Phasapon Manosukritkul ◽

Amonrat Kerdpardist ◽

Montree Saenlamool ◽

Ekalak Chaowicharat ◽

Amporn Poyai ◽

...

Keyword(s):

Electric Field ◽

Carrier Concentration ◽

Breakdown Voltage ◽

Bipolar Transistor ◽

Insulated Gate Bipolar Transistor ◽

Buried Layer ◽

Simulation Results ◽

Drift Layer

In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakdown voltage increased by approximately 30% compared with conventional NPT-TIGBT.

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Modeling and 2D Numerical Simulation of Transient Phenomena in Floating Body Soi Mosfets

MRS Proceedings ◽

10.1557/proc-490-239 ◽

1997 ◽

Vol 490 ◽

Author(s):

A. M. Ionescu ◽

F. Chaudier ◽

A. Chovet

Keyword(s):

Numerical Simulation ◽

Drain Current ◽

Analytical Models ◽

Floating Body ◽

Fully Depleted ◽

Transient Phenomena ◽

Simulation Based ◽

Original Contribution ◽

2D Numerical Simulation ◽

Current Transients

ABSTRACTThis paper presents a numerical-simulation-based investigation of drain current transients in floating body partially and fully depleted n-channel SOI MOSFETs. For both Zerbst-type and overshoot transients, analytical models are developed and validated. An original contribution concerns the detailed study of drain and source junction influences on the transient regime.

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Study of the side gate junctionless transistor in accumulation region

Microelectronics International ◽

10.1108/mi-03-2015-0027 ◽

2016 ◽

Vol 33 (2) ◽

pp. 61-67 ◽

Cited By ~ 2

Author(s):

Arash Dehzangi ◽

Farhad Larki ◽

Sawal Hamid Md Ali ◽

Sabar Derita Hutagalung ◽

Md Shabiul Islam ◽

...

Keyword(s):

Electric Field ◽

Drain Current ◽

Silicon On Insulator ◽

Valence Band Edge ◽

Content Type ◽

Force Microscopy ◽

Atomic Force ◽

Simulation Results ◽

Accumulation Region ◽

Tcad Sentaurus

Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

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The Effect of Oxide Fixed Charge on the Breakdown Characteristics of SiC Lateral Super Junction Devices

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.121-126.1585 ◽

2011 ◽

Vol 121-126 ◽

pp. 1585-1589 ◽

Cited By ~ 1

Author(s):

Hu Jun Jia ◽

Guo Dan Zhou ◽

Yin Tang Yang ◽

Bao Xing Duan

Keyword(s):

Electric Field ◽

Oxide Layer ◽

Breakdown Voltage ◽

Charge Compensation ◽

Fixed Charge ◽

Negative Effects ◽

Field Plate ◽

Negative Effect ◽

Simulation Results ◽

A Charge

In this paper, the positive and negative effects of oxide fixed charge on the breakdown characteristic of lateral SiC super junction devices are studied. Simulation results show that in the super junction devices with oxide layer, the negative (or positive) fixed charge on the SiO2/SiC interface act as a like p-pillar (or n-pillar) and enhance the depletion of n-pillar (or p-pillar), which result in a charge compensation and improvement of the breakdown characteristics of the devices. At the same time, a phenomenon of electric field crowding can be caused by the fixed charge and result in a decreasing of the breakdown voltage, this negative effect can be suppressed sufficiently by a field plate.

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Subthreshold Analytical Model of Asymmetric Gate Stack Triple Metal Gate All Around MOSFET (AGSTMGAAFET) for Improved Analog Applications

10.21203/rs.3.rs-360819/v1 ◽

2021 ◽

Author(s):

Arvind Ganesh ◽

Kshitij Goel ◽

Jaskeerat Singh Mayall ◽

Sonam Rewari

Keyword(s):

Electric Field ◽

Analytical Model ◽

Drain Current ◽

Simulation Software ◽

Current Gain ◽

Metal Gate ◽

Gate Stack ◽

Good Convergence ◽

Carrier Effect ◽

Simulation Results

Abstract In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal gate MOSFET(AGSTMGAAFET) and performed a comparative analysis with the simulation results obtained using the SILVACO 3D simulation software. Existing devices such as gate all around single metal (SMGAAFET), gate all around triple metal (TMGAAFET), gate stack single metal (GSSMGAAFET), gate stack triple metal (GSTMGAAFET) and asymmetric gate stack single metal (AGSTMGAAFET) have been compared with our proposed structure AGSTMGAAFET. Our device provides excellent performance in terms of drain current, transconductance, output conductance, current gain, maximum transducer power gain which shows our device’s suitability for various analog applications moreover the potential and electric field plots obtained have twostep profile and extremely low electric field near the drain region which ordains our device with the ability to suppress various SCE’s like DIBL and hot-carrier effect. The analytical model and simulation results show good convergence in values which validate the correctness of the proposed model.

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Simulation-Based Clarification of Appropriate Factors for Presenting Phosphene in Two Directions Avoiding Electrical Interference

Bioengineering ◽

10.3390/bioengineering8080111 ◽

2021 ◽

Vol 8 (8) ◽

pp. 111

Author(s):

Manami Kanamaru ◽

Phan Xuan Tan ◽

Eiji Kamioka

Keyword(s):

Visual Field ◽

Electric Field ◽

Support System ◽

Support Systems ◽

Alternating Current ◽

Blind People ◽

Simulation Based ◽

Simulation Results ◽

Electrical Interference

Walking support systems are essential for blind people. In this study, the presentation of phosphene position is focused on as a method to detect obstacles for blind people. When the phosphene is used in a walking support system, it is necessary to accurately present the phosphene in at least three directions of the visual field. Controlling the presentation of phosphene position has been reported in several previous studies. However, methodologies to present phosphene in multiple directions without any electric interference have not as yet been investigated. In this study, therefore, appropriate stimulation factors are clarified by the simulation of electric field on the eyeball surface which is strongly related to the presentation of phosphene position in the visual field. As a result of the simulation, it was revealed that the distance of each electrode does not give a significant effect to the eyeball surface. However, the phase of alternating current significantly changed the electric field on the eyeball surface. From investigation of the simulation results, it was clarified that the transition of the electric field on the eyeball surface can be controlled using anti-phase stimulation. In addition, the methodology to present the phosphene at least in two directions was verified.

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Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

Electronics ◽

10.3390/electronics8121553 ◽

2019 ◽

Vol 8 (12) ◽

pp. 1553

Author(s):

Runze Chen ◽

Lixin Wang ◽

Naixia Jiu ◽

Hongkai Zhang ◽

Min Guo

Keyword(s):

Breakdown Voltage ◽

Electric Potential ◽

Figure Of Merit ◽

Lower Electrode ◽

Simulation Results ◽

Improved Performance ◽

Result Analysis ◽

Floating Electrode

In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results.

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288 V-10 V DC- DC Converter Application Using AlGaN/GaN HFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.1321 ◽

2008 ◽

Vol 600-603 ◽

pp. 1321-1324 ◽

Cited By ~ 4

Author(s):

Seikoh Yoshida ◽

Mitsuru Masuda ◽

Yuki Niiyama ◽

Jiang Li ◽

Nariaki Ikeda ◽

...

Keyword(s):

Breakdown Voltage ◽

Conversion Efficiency ◽

Bridge Circuit ◽

Drain Current ◽

Switching Speed ◽

Large Current ◽

Constant Output ◽

Gan Hfet ◽

First Time ◽

Switching Wave

We report on the 288 V-10 V DC- DC converter circuit using AlGaN/GaN HFETs for the first time. The AlGaN/GaN HFET with a large current and a high breakdown voltage operation was fabricated. That is, the maximum drain current was over 50 A, and the minimum on-resistance was 70 mohm. The breakdown voltage was over 600 V. A DC-DC down-converter from input DC 288 V to output DC 10 V was fabricated using these HFETs. It was confirmed that the switching speed of the AlGaN/GaN HFET was faster than that of Si MOSFET. The DC-DC down-converter was fabricated using these HFETs. This converter was composed of a full bridge circuit using four n-channel AlGaN/GaN HFETs. In the case of AlGaN/GaN HFET, a gate switching wave (Vgs) and source-drain wave (Vds) were abrupt compared with those of using Si MOSFETs. In both cases, a stable and constant output DC 10V was also obtained and the conversion efficiency of the converters with AlGaN/GaN HFETs was 84%.

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