An Ultra-Low Power Holter and Low Complexity Design Using Mixed Signal Processor

2013 ◽  
Vol 284-287 ◽  
pp. 1627-1632
Author(s):  
Hsieh Chang Huang ◽  
Ching Tang Hsieh ◽  
Guang Lin Hsieh
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Ecg Signal ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sd Card ◽  
Signal Processor

An ultra-low power, portable, and easily implemented Holter recorder is necessary for patients or researchers of electrocardiogram (ECG). Such a Holter recorder with off-the-shelf components is realized with mixed signal processor (MSP) in this paper. To decrease the complexity of analog circuits and the interference of 60 Hz noise from power line, we use the MSP to implement a finite impulse response (FIR) filter which is equiripple design. We also integrate the ring buffer for the input samples and the symmetrical characteristic of the FIR filter for efficiently computing convolution. The experimental results show that the ECG output signal with the PQRST feature is easy to be distinguished. This ECG signal is recorded for 24 hours using a SD card. Furthermore, the ECG signal is transmitted with a smartphone via Bluetooth to decrease the burden of the Holter recorder. As a result, this paper uses the Lomb method for the spectral analysis of Heart Rate Variability (HRV) better than Fast Fourier Transform (FFT).

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

scholarly journals A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

2019 ◽  
Vol 17 ◽  
pp. 145-150
Author(s):  
Markus Scholl ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Calibration Method ◽  
Low Complexity ◽  
Frequency Stability ◽  
Wireless Communication Systems ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Digital Frequency ◽  
Frequency Calibration

Abstract. This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels. In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm ∘C−1 over a wide temperature range for temperature drifts of less than 1 ∘C s−1 with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

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