Design of a High Performance CMOS Bandgap Voltage Reference

2014 ◽  
Vol 981 ◽  
pp. 90-93
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Circuit Simulation ◽  
Absolute Temperature ◽  
Reference Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Changes ◽  
Bandgap Voltage Reference ◽  
Protection Circuit

Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

A High-Order CMOS Bandgap Voltage Reference

2014 ◽  
Vol 989-994 ◽  
pp. 1165-1168
Author(s):  
Qian Neng Zhou ◽  
Yun Song Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Power Supply Voltage ◽  
Power Supply Rejection Ratio ◽  
Voltage Deviation ◽  
Bandgap Voltage Reference

A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference

2020 ◽  
pp. 2150029
Author(s):  
Emad Ebrahimi ◽  
Maliheh Arabnasery
Keyword(s):  
Process Variations ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Reference ◽  
Op Amp ◽  
Offset Voltage ◽  
Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

3.48-nW 58.4ppm/∘C Sub-threshold CVR with Four Transistors and Two Resistors

2021 ◽  
Author(s):  
Mohammadreza Rasekhi ◽  
Emad Ebrahimi ◽  
Hamed Aminzadeh
Keyword(s):  
Process Variations ◽  
Mean Value ◽  
Absolute Temperature ◽  
Reference Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Low Power Cmos ◽  
Simulation Results ◽  
Cmos Voltage Reference

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach

2019 ◽  
Vol 17 (10) ◽  
pp. 777-783
Author(s):  
Shishu Pal ◽  
Ashutosh Nandi
Keyword(s):  
High Power ◽  
Power Supply ◽  
Circuit Simulation ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Supply Rejection

This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for start-up circuit. The measured settling time for output reference voltage is observed to be less than 4 μs. No filtering capacitor is used to improve the PSRR, which is –97 dB up to 1 MHz and subsequently reduces to –47.5 dB at 158 MHz.

A High-Performance Interface ASIC for Quartz Rate Sensor

2011 ◽  
Vol 483 ◽  
pp. 471-474
Author(s):  
Wei Ping Chen ◽  
Qing Yi Wang ◽  
Liang Yin ◽  
Zhi Ping Zhou
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Performance ◽  
Low Noise ◽  
Stable Operation ◽  
Cmos Process ◽  
Test Results ◽  
Bias Stability ◽  
Output Noise ◽  
Rate Sensor

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

DESIGN OF A CMOS BANDGAP REFERENCE CIRCUIT WITH A WIDE TEMPERATURE RANGE, HIGH PRECISION AND LOW TEMPERATURE COEFFICIENT

2014 ◽  
Vol 23 (08) ◽  
pp. 1450107 ◽  
Author(s):  
JUN-DA CHEN ◽  
CHENG-KAI YE
Keyword(s):  
Temperature Coefficient ◽  
High Precision ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Range ◽  
Wide Range ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Cmos Voltage Reference

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

A High Order Curvature-Compensated Bandgap Voltage Reference with a Novel Error Amplifier

2017 ◽  
Vol 26 (09) ◽  
pp. 1750127 ◽  
Author(s):  
Gongyuan Zhao ◽  
Mao Ye ◽  
Yiqiang Zhao ◽  
Kai Hu ◽  
Ruishan Xin
Keyword(s):  
Monte Carlo Simulation ◽  
Power Supply ◽  
Supply Voltage ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Dependent ◽  
Error Amplifier ◽  
Bandgap Voltage Reference ◽  
Simulation Results

This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, [Formula: see text]80[Formula: see text]dB power supply rejection (PSR) @1[Formula: see text]kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard [Formula: see text]m CMOS process, consuming 50[Formula: see text][Formula: see text]A at 25[Formula: see text]C with a supply voltage of 3.3[Formula: see text]V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18[Formula: see text]ppm/[Formula: see text]C over the temperature range from [Formula: see text]C to 120[Formula: see text]C. Monte Carlo simulation and Experimental Results validate the design.

The Design of Bandgap Reference Based on Empyrean Aether Software

2014 ◽  
Vol 687-691 ◽  
pp. 3489-3493
Author(s):  
Wei Qu ◽  
Li Mei Hou ◽  
Xiao Xin Sun ◽  
Jing Yu Sun ◽  
Liang Yu Li
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
Reference Voltage ◽  
Voltage Source ◽  
Reference Source ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Reference Voltage Source

A high-performance bandgap reference voltage source design method is proposed in this paper, according to the shortcomings of traditional bandgap reference voltage source. This method combined CSMC 0.35μm CMOS process with Aether software technology, enabling to improve the bandgap reference source op amp performance and take into account accuracy and stability of the system. From the experimental results: this bandgap reference voltage source output voltage has changed about 63 mV when the temperature varied from to , and the line regulator is 0.4mV/V when the power supply voltage varied from 3.2V to 3.3V. This system has advantages of high accuracy and good stability.

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