Drift-Free, 50 A, 10 kV 4H-SiC PiN Diodes with Improved Device Yields

The path to commericializing a 4H-SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.

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HIGH POWER, DRIFT-FREE 4H-SiC PIN DIODES

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156404002958 ◽

2004 ◽

Vol 14 (03) ◽

pp. 860-864 ◽

Cited By ~ 1

Author(s):

MRINAL K. DAS ◽

JOSEPH J. SUMAKERIS ◽

BRETT A. HULL ◽

JIM RICHMOND ◽

SUMI KRISHNASWAMI ◽

...

Keyword(s):

Carrier Lifetime ◽

Total Yield ◽

Pulsed Power ◽

Pin Diode ◽

Reduction Processes ◽

Dislocation Reduction ◽

Good Crystalline Quality ◽

Basal Plane Dislocation ◽

High Carrier ◽

High Degree

The path to commercializing a 4H - SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H - SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with V F as low as 3.9 V @ 100 A/cm2. These 10 kV diodes demonstrate pulsed current handling capability up to 328 A which represents over 3 MW of pulsed power. Furthermore, incorporation of two independent basal plane dislocation reduction reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability. The more benign LBPD 2 process yields wafers with better reverse blocking capability resulting in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm × 8.7 mm power PiN diode chips—the largest SiC chip reported to date.

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Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

Materials Science Forum ◽

10.4028/www.scientific.net/msf.1004.439 ◽

2020 ◽

Vol 1004 ◽

pp. 439-444

Author(s):

Yoshitaka Nishihara ◽

Koji Kamei ◽

Kenji Momose ◽

Hiroshi Osawa

Keyword(s):

Field Effect Transistor ◽

Minority Carrier ◽

Oxide Semiconductor ◽

Pin Diode ◽

Forward Voltage ◽

Carrier Recombination ◽

Crucial Problem ◽

Basal Plane Dislocation ◽

Effect Transistor ◽

Voltage Degradation

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

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16 kV, 1 cm2, 4H-SiC PiN Diodes for Advanced High-Power and High-Temperature Applications

Materials Science Forum ◽

10.4028/www.scientific.net/msf.740-742.895 ◽

2013 ◽

Vol 740-742 ◽

pp. 895-898 ◽

Cited By ~ 11

Author(s):

Lin Cheng ◽

Anant K. Agarwal ◽

Michael J. O'Loughlin ◽

Craig Capell ◽

Khiem Lam ◽

...

Keyword(s):

Carrier Lifetime ◽

Voltage Drop ◽

Injection Current ◽

Pin Diode ◽

Forward Voltage ◽

Average Temperature ◽

Forward Voltage Drop ◽

Current Densities ◽

High Level ◽

Injection Current Density

In this work, we report our recently developed 16 kV, 1 cm2, 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×1014/cm3 doped n-type SiC drift layer with a device active area of 0.5175 cm2. Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (JF) of 350 ~ 400 A/cm2, the differential on-resistance (RON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm2 at 20°C to 5.12 mΩ·cm2 at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm2/°C, while the forward voltage drop (VF) at 100 A/cm2 reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower RON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

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Influence of in-Grown Stacking Faults on Electrical Characteristics of 4H-SiC Pin Diode with Long Carrier Lifetime

Materials Science Forum ◽

10.4028/www.scientific.net/msf.740-742.903 ◽

2013 ◽

Vol 740-742 ◽

pp. 903-906 ◽

Cited By ~ 5

Author(s):

Koji Nakayama ◽

Atsushi Tanaka ◽

Katsunori Asano ◽

Tetsuya Miyazawa ◽

Hidekazu Tsuchida

Keyword(s):

Room Temperature ◽

Carrier Lifetime ◽

Stacking Faults ◽

Pin Diode ◽

Electrical Characteristics ◽

Forward Voltage ◽

Pin Diodes ◽

Voltage Drops ◽

Implantation Process ◽

Drift Layer

The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z1/2center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.

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12 kV 4H-SiC p-IGBTs with Record Low Specific On-Resistance

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.1187 ◽

2008 ◽

Vol 600-603 ◽

pp. 1187-1190 ◽

Cited By ~ 22

Author(s):

Q. Jon Zhang ◽

Charlotte Jonas ◽

Joseph J. Sumakeris ◽

Anant K. Agarwal ◽

John W. Palmour

Keyword(s):

Carrier Lifetime ◽

Drift Region ◽

Gate Bias ◽

Enhancement Layer ◽

Channel Mobility ◽

Dc Characteristics ◽

Blocking Voltage ◽

High Carrier ◽

P Type ◽

First Time

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

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High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.841 ◽

2014 ◽

Vol 778-780 ◽

pp. 841-844 ◽

Cited By ~ 1

Author(s):

Koji Nakayama ◽

Shuji Ogata ◽

Toshihiko Hayashi ◽

Tetsuro Hemmi ◽

Atsushi Tanaka ◽

...

Keyword(s):

High Voltage ◽

Recovery Time ◽

Carrier Lifetime ◽

Low Voltage ◽

Reduction Rate ◽

Drift Region ◽

Pin Diode ◽

Fully Depleted ◽

Fast Switching ◽

Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

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Minority‐carrier lifetime in gold‐diffused silicon at high carrier concentrations

Journal of Applied Physics ◽

10.1063/1.331542 ◽

1982 ◽

Vol 53 (9) ◽

pp. 6250-6252 ◽

Cited By ~ 14

Author(s):

W. Schmid ◽

J. Reiner

Keyword(s):

Carrier Lifetime ◽

Minority Carrier ◽

Minority Carrier Lifetime ◽

High Carrier

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Local Lifetime Control in 4H-SiC by Proton Irradiation

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.436 ◽

2018 ◽

Vol 924 ◽

pp. 436-439 ◽

Cited By ~ 2

Author(s):

Pavel Hazdra ◽

Stanislav Popelka ◽

Adolf Schöner

Keyword(s):

Low Temperature ◽

Proton Irradiation ◽

Carrier Lifetime ◽

Carrier Dynamics ◽

Pin Diode ◽

Radiation Defects ◽

Excess Carrier ◽

Low Temperature Annealing ◽

Irradiation Energy ◽

Proton Implantation

The effect of local lifetime control by proton irradiation on the OCVD response of a 10 kV SiC PiN diode was investigated. Carrier lifetime was reduced locally by irradiation with 800 keV protons at fluences up to 1x1011cm-2. Radiation defects were characterized by DLTS and C-V profiling; excess carrier dynamics were measured by the OCVD and analyzed using the calibrated device simulator ATLAS from Silvaco, Inc. Results show that proton implantation followed by low temperature annealing can be used for controllable local lifetime reduction in SiC devices. The dominant recombination centre is the Z1/2defect, whose distribution can be set by irradiation energy and fluence. The local lifetime reduction, which improves diode recovery, can be monitored by OCVD response and simulated using the SRH model accounting for the Z1/2defect.

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Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.272 ◽

2019 ◽

Vol 963 ◽

pp. 272-275

Author(s):

Yoshitaka Nishihara ◽

Koji Kamei ◽

Kenji Momose ◽

Hiroshi Osawa

Keyword(s):

Silicon Carbide ◽

Basal Plane ◽

Near Infrared ◽

Minority Carrier ◽

Pin Diode ◽

Forward Voltage ◽

Carrier Recombination ◽

Near Ultraviolet ◽

Bipolar Devices ◽

Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

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