scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

2011 ◽  
pp. 196-202
Author(s):  
P.Sasi Bala ◽  
S. Raghavendra
Keyword(s):  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Alpha Power ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance ◽  
Least Significant Bits

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic.By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai’s alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

2016 ◽  
pp. 90-95
Author(s):  
M. Suhasini ◽  
K. Prabhu Kumar ◽  
P. Srinivas
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Performance Estimation ◽  
Switching Activity ◽  
Distributed Arithmetic ◽  
Hybrid Type ◽  
Arithmetic Algorithm ◽  
Overall Performance ◽  
Sign Extension ◽  
And Performance

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

WATT MATTERS MOST? DESIGN SPACE EXPLORATION OF HIGH-PERFORMANCE MICROPROCESSORS FOR POWER-PERFORMANCE EFFICIENCY

2007 ◽  
Vol 16 (03) ◽  
pp. 357-378
Author(s):  
PEDRO TRANCOSO
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
High Sensitivity ◽  
Clock Frequency ◽  
Power Performance ◽  
Large Power ◽  
Multiple Parameters ◽  
And Performance ◽  
The One ◽  
Power Awareness

Computer systems have evolved significantly in the last years leading to high-performance systems. This, however, has come with a cost of large power dissipation. As such, power-awareness has become a major factor in processor design. Therefore, it is important to have a complete understanding of the power and performance behavior of all processor components. In order to achieve this, the current work presents a comprehensive analysis of power-performance efficiency for different high-end microarchitecture configurations using three different workloads: multimedia, scientific, and database. The objectives of this work are: (1) to analyze and compare the power-performance efficiency for different workloads; (2) to present a sensitivity analysis for the microarchitecture parameters in order to identify which ones are more sensitive to changes in terms of power-performance efficiency; and (3) to propose power-performance efficient configurations for each workload. The simulation results show that the multimedia workload is the one achieving the highest efficiency but the database workload is the most sensitive to parameter changes. In addition, the results also show that the parameter sensitivity depends significantly on the workload. While the issue width and clock frequency present very high sensitivity across all workloads (approximately 100%), for the database workload, the first-level instruction cache size shows an even higher sensitivity (149%). The correct configuration of these microarchitecture parameters is essential. A careless configuration of a single parameter from a baseline setup may result in a loss of the power-performance efficiency of up to 99%. Finally, carefully tuning multiple parameters simultaneously may result in gains up to 154% over the power-performance efficiency of the baseline configuration.

scholarly journals Silicon photonics devices for integrated analog signal processing and sampling

Nanophotonics ◽  
2014 ◽  
Vol 3 (4-5) ◽  
pp. 313-327 ◽  
Author(s):  
Steven Spector ◽  
Cheryl Sorace-Agaskar
Keyword(s):  
Signal Processing ◽  
Silicon Photonics ◽  
High Speed ◽  
Analog Signal Processing ◽  
Photonic Devices ◽  
Analog Signal ◽  
Optical Systems ◽  
Analog To Digital ◽  
And Performance ◽  
Analog Systems

AbstractSilicon photonics offers the possibility of a reduction in size weight and power for many optical systems, and could open up the ability to build optical systems with complexities that would otherwise be impossible to achieve. Silicon photonics is an emerging technology that has already been inserted into commercial communication products. This technology has also been applied to analog signal processing applications. MIT Lincoln Laboratory in collaboration with groups at MIT has developed a toolkit of silicon photonic devices with a focus on the needs of analog systems. This toolkit includes low-loss waveguides, a high-speed modulator, ring resonator based filter bank, and all-silicon photodiodes. The components are integrated together for a hybrid photonic and electronic analog-to-digital converter. The development and performance of these devices will be discussed. Additionally, the linear performance of these devices, which is important for analog systems, is also investigated.

Development of High Performance Moisture Separator Reheater

2009 ◽  
Author(s):  
Issaku Fujita ◽  
Kotaro Machii ◽  
Teruaki Sakata
Keyword(s):  
High Speed ◽  
Nuclear Power ◽  
High Performance ◽  
Power Plants ◽  
Tube Bundle ◽  
Separation Performance ◽  
Heating Steam ◽  
Severe Erosion ◽  
Moisture Separator ◽  
And Performance

Moisture Separator Reheaters (MSRs) of Nuclear power plants, especially 1st generation type (commercial operation started from between 1970 and 1982), has been suffered from various problems like severe erosion, moisture separation performance deterioration, drain sub cooling. To solve these problems and performance improvement, improved MSR was developed. At the new MSR, high performance SS439 stainless steel round type tube bundle was applied, where heating steam distribution is optimized by orifice plate in order to minimize the drain sub cooling. Based on the CFD approach, cycle steam distribution was optimized and FAC resistant material application for the internal parts of MSRs was determined. As a result, pressure drop was reduced by 0.6% against the HP turbine exhaust pressure. Performance of moisture separation was improved by the latest chevron type separator. Where, the reverse pressure is locally caused at the drainage area of the separator because remarkable longitudinal pressure distribution is formed by the high-speed steam flow in the manifold. Then, a new moisture separation structure was developed in consideration of the influence that this reverse pressure gave to the separator performance.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

scholarly journals Compact Radar Cross-Section Measurement Setup and Performance Evaluation

2021 ◽  
Vol 19 ◽  
pp. 147-152
Author(s):  
Maximilian F. Sundermeier ◽  
Dirk Fischer
Keyword(s):  
Signal Processing ◽  
Cross Section ◽  
Digital Signal ◽  
Radar Cross Section ◽  
Calibration Procedure ◽  
Calibration Target ◽  
Improve Measurement ◽  
Anechoic Chambers ◽  
Overall Performance ◽  
And Performance

Abstract. Radar cross-section measurements require the background reflections to be much lower than the reflections of the device under test. Although, anechoic chambers with special target holders meet this requirement, they are expensive and still have imperfections. To further reduce background reflections or to measure in environments where an anechoic chamber is not suitable, digital signal processing can be used to reduce background reflections. In this paper, a complete signal processing chain realized in Matlab is proposed, involving time gating of the measured target response and a background subtraction technique. Furthermore, the proposed signal processing includes a calibration procedure with either a single known calibration target or multiple known targets to improve measurement uncertainties. A compact measurement setup, consisting of a vector network analyzer and two horn antennas, is used to evaluate the overall performance and the advantages of a multiple known target calibration in a practical manner. The calibrated setup is able to measure the radar cross-section in a frequency range from 2 to 12 GHz with a mean error of less than 0.2 dB for both, VV and HH polarization combinations. It could also be shown, that a multi target calibration can result in an improvement of the measurement uncertainty by about 2.5 %.

scholarly journals IMPLEMENTATION OF A REDUCED COMPLEXITY HIGH PERFORMANCE DATA ACQUISITION CHIP USING 0.18 MICRON TECHNOLOGY

2021 ◽  
Vol 7 (3) ◽  
pp. 22-26
Author(s):  
Hai P. Le ◽  
◽  
Aladin Azyegh ◽  
Jugdutt Singh ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Data Acquisition ◽  
High Speed ◽  
High Performance ◽  
Modern Science ◽  
Digital Data ◽  
Clock Frequency ◽  
Flash Adc ◽  
Analog Signals ◽  
Wide Range

Data acquisition (DAQ) in the general sense is the process of collecting information from the real world. For engineers and scientists, this data is mostly numerical and is usually collected, stored and analysed using computers. However, most of the input signals cannot be read directly by digital computers. Because they are generally analog signals distinguished by continuous values, while computers can only recognise digital signals containing only the on/off levels. DAQ systems are therefore inevitably necessary, as they include the translation requirements from analog signals to digital data. For this reason, they have become significant in wide range of applications in modern science and technology [1]. The paper precents the disign of a 12-bit high-speed low-power Data Acquisition (DAQ) Chip. In this paper, the disigns of the building block components are aimed at high-accuracy along with high-speed and low power dissipation. A modifided flash Analog-to-Digital converter (ADC) was used instead of the traditional flash proposed DAQ chip operates at 1 GHz master clock frequency and achieves a sampling speed of 125 MS/s. It dissipates only 64.9 mW of power as compared to 97.2 mW when traditional flash ADC was used.

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation

2019 ◽  
Vol 28 (14) ◽  
pp. 1950237
Author(s):  
Ling Zheng ◽  
Zhiliang Qiu ◽  
Weina Wang ◽  
Weitao Pan ◽  
Shiyong Sun ◽  
...  
Keyword(s):  
High Throughput ◽  
Network Flow ◽  
High Speed ◽  
High Performance ◽  
Clock Frequency ◽  
Pipeline Architecture ◽  
Exact Matching ◽  
Flow Classification ◽  
Rule Sets ◽  
Bit Vector

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[Formula: see text]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

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