Computation of Constant Gain and NF Circles for 60 GHz Ultra-low noise Amplifiers

Wireless communication is a constantly evolving and forging domain. The action of the RF input module is critical in the radio frequency signal communication link. This paper discusses the design of a RF high frequency transistor amplifier for unlicensed 60 GHz applications. The Transistor used for analysis is a FET amplifier, operated at 60GHz with 10 mA at 6.0 V. The simulation of the amplifier is made with the Open Source Scilab 6.0.1 console software. The MESFET is biased such that Sll = 0.9<30°, S12 = 0.21<-60°, S21= 2.51<-80°, and S22 = 0.21<-15o. It is found that the transistor is unconditionally stable and hence unilateral approximation can be employed. With these assumptions, the maximum value of source gain of the amplifier is found to be at 7.212 dB and the various constant source gain circles and noise figure circles are computed. The transistor has the following noise parameters: Fmin = 3 dB, Rn = 4 Ω, and Γopt = 0.485<155°. The amplifier is designed to have an input and output impedance of 50 ohms which is considered as the reference impedance.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

Measuring of an unknown voltage by using single electron transistor based voltmeter

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.