Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

Study of a MOEMS XOR gate based on optical ring resonator

Based on ring resonator with Microelectromechanical systems, optical XOR logic gate is proposed in this paper to realize the optical logic gate application. The proposed gate is basically structured on an optical ring resonator with 7µm radius and resonance wavelength of 1.55µm which is placed on the edge of a thin SiC circular diaphragm. In order to apply input voltages to electrodes, two very thin circular gold layers with 50nm air gap spacing are deposited under the diaphragm. Input voltages are considered as logic inputs and resonance wavelength shift as logic output. When an input DC voltage is applied across the diaphragm, an attractive electrostatic force is created between two electrodes. As a result, the diaphragm is deformed and an internal stress is created. This in turn changes the resonator refractive index due to the photoelastic effect and thus shifts its resonance wavelength about 35nm. COMSOL Multiphysics and MATLAB are carried out to verify FEA and numerical analysis of the designed structure, respectively. A good agreement between the simulations and analytical results is obtained. Enhancement of the wavelength shift and FSR are resulted. The proposed structure is used as an optical XOR gate for the first time.

Threshold Logic Technology based E-cube Routing on a 4-dimensional hypercube

Hypercube network connection is formed by connecting different N number of nodes that are expressed as a power of 2. If each node has an address of m bits then the total number of nodes in the Hypercube network is N=2^m. In calculating the predefined routing path for the case of this E-cube network, we apply deterministic algorithm which gives a deadlock free concept. For determining predefined routing path, node addresses involved in the path are calculated by using the exclusive operation, firstly, on the node addresses of source and destination, next, on the derived nodes according to the algorithm. In the present work, the Exclusive-OR operation is performed with the help of electron-tunneling based XOR gate which is made up of Multiple input threshold logic gate. This multiple input threshold logic gate technology is really different from the existing one. By using an emerging technology we are capable of making an electronic circuit with high speed, low cost, high concentration density, light in weight, reduced gate numbers and low power consumption. This technology is relies on the condition of linear threshold logic and electron-tunneling event. When we are interested in implementing a circuit, a multi-inputs but one-output based logic-gate will be taken account of consideration. In this work, we have designed an E-cube Routing on a 4-dimensional hypercube to find out the node addresses for predefining the deadlock free routing path from source to destination. To develop this “E-cube Routing on a 4-dimensional hypercube”, we must require a specific logic called Exclusive-OR gate and for this, some small components like 2-input OR gate, 2-input AND gates of different input conditions are essential. After arranging this XOR gate in a pattern discussed in section 2, a desired circuit is implemented. All the circuit we are intended to construct are given in due places with their threshold logic and simulation set, the simulation results are provided as well. Different truth tables, derivation of threshold logic expressions are given for clear understanding. We have taken our consideration of whether the present work circuits are faster or slower than the circuits of CMOS based- and Single electron transistor (SET) based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 10meV to 250meV which is very small amount. All the combinational circuits we have presented in this work are of ‘generic multiple input threshold logic gate’-based.

FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Transcriptional interference in toehold switch-based RNA circuits

Gene regulation based on regulatory RNA is an important mechanism in cells and is increasingly used for regulatory circuits in synthetic biology. Toehold switches are rationally designed post-transcriptional riboregulators placed in the 5' untranslated region of mRNA molecules. In the inactive state of a toehold switch, the ribosome-binding site is inaccessible for the ribosome. In the presence of a trigger RNA molecule protein production is turned on. Using antisense RNA against trigger molecules (anti-trigger RNA), gene expression can also be switched off again. We here study the utility and regulatory effect of antisense transcription in this context, which enables a particularly compact circuit design. Our circuits utilize two inducible promoters that separately regulate trigger and anti-trigger transcription, whereas their cognate toehold switch, regulating expression of a reporter protein, is transcribed from a constitutive promoter. We explore various design options for the arrangement of the promoters and demonstrate that the resulting dynamic behavior is strongly influenced by transcriptional interference (TI) effects, leading to more than four-fold differences in expression levels. Our experimental results are consistent with previous findings that enhanced local RNA polymerase concentrations due to active promoters in close proximity lead to an increase in transcriptional activity of the strongest promoter in the circuits. Based on this insight, we selected optimum promoter designs and arrangements for the realization of a genetic circuit comprised of two toehold switches, two triggers and two anti-triggers that function as a post-transcriptional RNA regulatory exclusive OR (XOR) gate.

Fanout of 2 Triangle Shape Spin Wave Logic Gates

Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x.