Dual mode Bluetooth Controller via PCM-CODEC Interface for Audio Application

Bluetooth may be an inaccessible development standard utilized for exchanging data between settled and flexible contraptions over brief divisions utilizing UHF radio waves within the mechanical, coherent, and restorative radio bunches, from 2.402GHz to 2.480 GHz. PCM codec is an A/D interface for speech signals. The Bluetooth center framework underpins co-ordinate transport of application information that’s isochronous and of a consistent rate (either bit-rate or frame-rate for pre-framed information) employing an SCO or ESCO consistent joins. These coherent joins save physical channel transfer speed and give a consistent rate of transport bolted to the piconet clock. The codec interface block is used to interface an external PCM (8KHz voice data) or a stereo codec with the baseband controller for the direct transfer of voice data on isochronous links to external CODEC. Bluetooth baseband supports two CODEC interface protocols 1) for audio links it is the PCM interface and 2) for mono/stereo music data from audio codec it uses the IIS interface. This enables the source of isochronous data to be directly interfaced to the baseband controller if it is not required to be processed by firmware. It also provides the host access path where the source of isochronous data will be any application running on the host and data is written and read directly into baseband SCO/ESCO FIFOs from firmware. In this paper, PCM is verified in the Cadence tool and simulated images are shown.

Ultra Low Frequency Wide Band Low Pass Active Filter for Bio-Medical Applications Simulated on Cadence tool

An ultra low frequency wide band low pass active filter is designed and simulated on 180nm cadence virtuoso tool for biomedical applications in this paper. This proposed designed low pass active filter is being able to stop low frequency signal of µHz and can pass up to Hz using the CMOS nanotechnology. This is a second order low pass active filter. It can be useful to identify the human disease by detecting ultra low frequency bio-signal. The simulated result shows ultra low power consumption of 200pW with high bandwidth at 1mV input supply.

Second Order Low Pass RC Active Filter for Low Frequency Signal Processing

The different parameters define the characteristics of filter for various applications like: Biomedical applications, Defense communication systems, Wireless Communication systems etc. The mostly measured parameters for filter designing are frequency range, cut off frequency, gain, power consumption, and noise. In this paper, our work focuses on frequency range measurement at cut off frequency of Hz of second order low pass filter with designed using CMOS technology for IC fabrication. The proposed circuit gives the high frequency range at low frequency (100Hz – 10MHz) with 1mV 50Hz low power supply using complementary compound pair on the value of R=1K and C=10pH. This second order active low pass filter provides high amplification at the output with 4.861V. It is implemented and simulated on 180nm Cadence tool in terms of wide frequency range or band at cut off frequency of Hz to MHz.

Design and Implementation of Vlsi Architecture for Arrhythmia Detection

Arrhythmia is one in all the foremost well-liked heart diseases that might result in serious consequences. In case of arrhythmia, the heart rate may be either too fast or slow. When a person suffers from arrhythmic the heart may not pump sufficient blood to all body parts that is necessary for circulation. some of the symptoms of arrhythmia includes faintness ,fluttering your chest, a light headedness or dizziness, fainting or near fainting and on the worst it may turn out to be deadly causing ventricular fibrillation. Due to this it is very crutial to detect conditions of arrhythmia. It is very difficult to identify the symptoms of arrhythmia from a long ECG record. This projects presents a VLSI based design of high speed and minimum area for arrhythmia detection .It uses arithmetic distribution discrete wavelet transform for arrhythmia detection of QRS wave and is implemented using CADENCE. The purpose of distributive arithmetic discrete wavelet change is to compress the ECG signal. ECG signals are generated via MATLAB. The resultant of these coefficients are given to the LUT, which comprises of MIT-BIH databases. Our aim is to detect the QRS complex in the ECG signal and to identify the time and frequency variations. By comparing these variations with that of the reference variations produced in the normal ECG waveform it is easy to identify whether the patient is suffering from arrhythmia or not. The coding was written in verilog and stimulated in modelsim software and implemented using CADENCE tool.

Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications

In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive approximation algorithm runs over several clock cycles for analog to digital conversion. Power usage and complexity of the circuit is minimized by low conversion rate i.e permitting one clock for each bit in the proposed method.

Implementation of full Adder with 2x1 Mux using Optimised Gdi Technique

The major considerations of any digital circuit are area and power consumption. GDI (Gate Diffusion Input) - an advanced technique is proposed for designing a circuit in order to reach the requirements, reduce power consumption, and effective utilization of area. Despite having many uses, the GDI technique is noted for some drawbacks. The principle point of this paper is to concentrate on the downsides of the existing GDI technique and to propose an improved version of GDI technique to withstand the disadvantages of the earlier one. A full adder with 2x1 MUX is designed using conventional techniques and compared their simulation results with full adder using optimized GDI technique. Simulation and analysis of the full adder are carried out using CADENCE tool at 45nm technology. Simulation results proved that the proposed design had improved the performance of GDI and reduces almost less than 50% of layout area and power consumption is only 1.5% of the power consumed using conventional technique.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Design of Dadda and Wallace Tree Multiplier Using Compressor Technique

The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.