ScienceGate
Advanced Search
Author Search
Journal Finder
Blog
Sign in / Sign up
ScienceGate
Search
Author Search
Journal Finder
Blog
Sign in / Sign up
2008 IEEE International High Level Design Validation and Test Workshop
Latest Publications
TOTAL DOCUMENTS
44
(FIVE YEARS 0)
H-INDEX
3
(FIVE YEARS 0)
Published By IEEE
9781424429226
Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
Related Keywords
Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
Related Keywords
Panel: SoC power management implications on validation and testing
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695890
◽
2008
◽
Author(s):
Bhanu Kapoor
◽
John Goodenough
◽
Shankar Hemmady
◽
Shireesh Verma
◽
Manuel A. d'Abreu
◽
...
Keyword(s):
Power Management
◽
Management Implications
Download Full-text
Applications of decorator and observer design patterns in functional verification
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695867
◽
2008
◽
Cited By ~ 1
Author(s):
Farzin Karimi
Keyword(s):
Design Patterns
◽
Observer Design
◽
Functional Verification
Download Full-text
Timing verification of distributed network systems at higher levels of abstraction
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695884
◽
2008
◽
Author(s):
Hassan Hatefi-Ardakani
◽
Amir Masoud Gharehbaghi
◽
Shaahin Hessabi
Keyword(s):
Distributed Network
◽
Timing Verification
◽
Levels Of Abstraction
◽
Network Systems
Download Full-text
A HW/SW co-simulation framework for the verification of multi-CPU systems
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695888
◽
2008
◽
Cited By ~ 3
Author(s):
S. Cordibella
◽
F. Fummi
◽
G. Perbellini
◽
D. Quaglia
Keyword(s):
Simulation Framework
Download Full-text
Temporal parallel gate-level timing simulation
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695886
◽
2008
◽
Cited By ~ 2
Author(s):
Dusung Kim
◽
Maciej Ciesielski
◽
Kyuho Shim
◽
Seiyang Yang
Keyword(s):
Timing Simulation
Download Full-text
On Chip Instrument application to SoC analysis
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695879
◽
2008
◽
Author(s):
Neal Stollon
Keyword(s):
On Chip
Download Full-text
On dynamic switching of navigation for semi-formal design validation
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695873
◽
2008
◽
Cited By ~ 1
Author(s):
Ankur Parikh
◽
Michael S. Hsiao
Keyword(s):
Design Validation
◽
Dynamic Switching
◽
Formal Design
Download Full-text
Session 2: Test
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695868
◽
2008
◽
Download Full-text
Injecting intermittent faults for the dependability validation of commercial microcontrollers
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695899
◽
2008
◽
Cited By ~ 9
Author(s):
D. Gil
◽
L.J. Saiz
◽
J. Gracia
◽
J.C. Baraza
◽
P.J. Gil
Keyword(s):
Intermittent Faults
Download Full-text
Test and validation of a non-deterministic system — True Random Number Generator
2008 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2008.4695881
◽
2008
◽
Cited By ~ 2
Author(s):
Kapila Udawatta
◽
Mehdi Ehsanian
◽
Sergey Maidanov
◽
Surya Musunuri
Keyword(s):
Random Number
◽
Random Number Generator
◽
Deterministic System
◽
Number Generator
◽
True Random Number Generator
Download Full-text
Load More ...
Sign in / Sign up
Close
Export Citation Format
Close
Share Document
Close