Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

Super-Conducting Quantum Interference Device Technique: 3-D Localization of a Short within a Flip Chip Assembly

In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

Single Point PICA Probing with an Avalanche Photo-Diode

For time resolved hot carrier emission from the backside, an alternate approach is demonstrated termed single point PICA. The single point approach records time resolved emission from an individual transistor using time-correlated-single-photon counting and an avalanche photo-diode. The avalanche photo-diode has a much higher quantum efficiency than micro-channel plate photo-multiplier tube based imaging cameras typically used in earlier approaches. The basic system is described and demonstrated from the backside on a ring oscillator circuit.

X-Ray Nanotomography (XRMT) Tool for Non-Destructive High-Resolution Imaging of ICs

A high-resolution table-sized x-ray nanotomography (XRMT) tool has been constructed that shows the promise of nondestructively imaging the internal structure of a full IC stack with a spatial resolution better than 100 nm. Such a tool can be used to detect, localize, and characterize buried defects in the IC. By collecting a set of X-ray projections through the full IC (which may include tens of micrometers of silicon substrate and several layers of Cu interconnects) and applying tomographic reconstruction algorithms to these projections, a 3D volumetric reconstruction can be obtained, and analyzed for defects using 3D visualization software. XRMT is a powerful technique that will find use in failure analysis and IC process development, and may facilitate or supplant investigations using SEM, TEM, and FIB tools, which generally require destructive sample preparation and a vacuum environment.

Optical Waveform Probing – Strategies for Non-Fllpchlp Devices and Other Applications

Optical waveform probing is a critical component in flipchip diagnostics. There is a dramatic increase in the need for backside silicon probing of non-flipchip packaged devices. The effective way to implement this strategy is to package the die in a BGA carrier that allows backside analysis. Optical waveform probing has been used primarily as a digital waveform timing analysis tool. The capability of optical waveform probers can be extended to failsite isolation and qualitative analog signal analysis.

Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

TEM Examination of a Specified Site Identified by X-SEM in Microelectronics Failure Analysis

In semiconductor failure analysis, there is a demand that after mechanical polishing and scanning electron microcopy (SEM) examination, the failure site needs to be analyzed by transmission electron microscope (TEM) for a detailed examination to find the root cause. In this paper, a fast and practical TEM sample preparation method for TEM examination of specific site identified by cross-section scanning electron microscope (SEM) is demonstrated for further structural analysis.

Backside Etch: A New FA Technique for Gate Oxide Pinhole and Si Defect Identification for Power IC Devices

The present paper describes a backside F/A technique that identifies power IC devices’ Iqcc (quiescent Vcc current) failure mechanisms. Choline hydroxide[1, 2] is used to expose the entire die back, keeping gate oxide intact. The perspective gained from the backside etch allows an analyst to quantitatively observe gate oxide defects as well as Si defects. It is discovered that either one of them can cause the same Iqcc failure. More than 60 dice can be prepared on one specimen in 2-3 hrs. Another advantage of this technique over conventional top delayering or precision crosssection process is that no SEM work is necessary, only optical microscope is needed to identify defects with typical size of 0.1 μm.

Signal Trace and Power Plane Shorts Fault Isolation Using TDR

The focus of this article is on locating signal-to-ground shorts and plane-to-plane shorts using the time domain reflectometry (TDR) based fault isolation system. The article proposes two comparative techniques for plane-to-plane short location, both based on the secondary information in the TDR data. The first technique looks for the difference in secondary reflections in the TDR waveform and the second looks at the inductance of the current return path, which can be computed in IConnect TDR software. The article presents simple test board example for plane-to-plane short failure location and discusses the results obtained by applying the TDR technique to the measurements of a sample package under test. Locating a signal-to-ground short has been shown to present little difficulty over a comparable open fault locating task. However, with the true impedance profile and planar inductance analyses, the claim of impossibility of locating a plane-to-plane is effectively challenged in this paper.

Evaluation of Alternative Preparation Methods for Failure Analysis at Modern Chip and Package Technologies

We evaluated laser ablation and sandblasting as preparation methods for package related failures and for backside analysis of ICs. With laser ablation we uncovered gold wedges on an internal board of a PLFBGA package without damage of the gold wires and the board metallization. This was possible by optimization of the laser pulse energy and the pulse repetition rate and by limitation of the ablation area. Sandblasting showed to be a gentle way for backside thinning down to 60 μm silicon thickness. For a surface smoothness sufficient for IR imaging a subsequent planarization treatment is necessary.