Proceedings of 1997 International Symposium on Low Power Electronics and Design
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131

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LVDCSL: low voltage differential current switch logic, a robust low power DCSL family

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621201 ◽

2002 ◽

Author(s):

D. Somasekhar ◽

K. Roy

Keyword(s):

Low Power ◽

Low Voltage ◽

Current Switch ◽

Differential Current

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Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621289 ◽

2002 ◽

Author(s):

R.V.K. Pillai ◽

D. Al-Khalili ◽

A.J. Al-Khalili

Keyword(s):

Floating Point ◽

Switch Architectures

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Fully depleted CMOS/SOI device design guidelines for low power applications

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621303 ◽

2002 ◽

Author(s):

S.R. Banna ◽

P.C.H. Chan ◽

M. Chan ◽

S.K.H. Fung ◽

P.K. Ko

Keyword(s):

Low Power ◽

Design Guidelines ◽

Device Design ◽

Fully Depleted

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SOI CMOS as a mainstream low-power technology: a critical assessment

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621302 ◽

2002 ◽

Author(s):

D.A. Antoniadis

Keyword(s):

Low Power ◽

Critical Assessment ◽

Soi Cmos

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A gate resizing technique for high reduction in power consumption

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621299 ◽

2002 ◽

Author(s):

P. Girard ◽

C. Landrault ◽

S. Pravossoudovitch ◽

D. Severac

Keyword(s):

Power Consumption ◽

High Reduction ◽

Gate Resizing

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Power reduction techniques for a spread spectrum based correlator

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621287 ◽

2002 ◽

Author(s):

D. Garrett ◽

M. Stan

Keyword(s):

Spread Spectrum ◽

Power Reduction ◽

Reduction Techniques

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A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621286 ◽

2002 ◽

Cited By ~ 1

Author(s):

Hyung-Joon Kwon ◽

Kwyro Lee

Keyword(s):

Low Power ◽

Partial Remainder

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Dynamic algorithm transformations (DAT) for low-power adaptive signal processing

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621271 ◽

2002 ◽

Cited By ~ 5

Author(s):

M. Goel ◽

N.R. Shanbhag

Keyword(s):

Signal Processing ◽

Low Power ◽

Adaptive Signal Processing ◽

Dynamic Algorithm ◽

Power Adaptive ◽

Algorithm Transformations ◽

Adaptive Signal

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A method of redundant clocking detection and power reduction at RT level design

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621261 ◽

2002 ◽

Author(s):

M. Ohnishi ◽

A. Yamada ◽

H. Noda ◽

T. Kambe

Keyword(s):

Power Reduction ◽

Level Design

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Formalized methodology for data reuse exploration in hierarchical memory mappings

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1997.621203 ◽

2002 ◽

Author(s):

J.P. Diguet ◽

W.F. Catthoor ◽

H. De Man

Keyword(s):

Data Reuse ◽

Hierarchical Memory

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Proceedings of 1997 International Symposium on Low Power Electronics and DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM

LVDCSL: low voltage differential current switch logic, a robust low power DCSL family

Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition

Fully depleted CMOS/SOI device design guidelines for low power applications

SOI CMOS as a mainstream low-power technology: a critical assessment

A gate resizing technique for high reduction in power consumption

Power reduction techniques for a spread spectrum based correlator

A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications

Dynamic algorithm transformations (DAT) for low-power adaptive signal processing

A method of redundant clocking detection and power reduction at RT level design

Formalized methodology for data reuse exploration in hierarchical memory mappings

Proceedings of 1997 International Symposium on Low Power Electronics and Design
Latest Publications