Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07
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Published By ACM Press

9781595936226

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Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231973 ◽

2007 ◽

Cited By ~ 6

Author(s):

Hoyeol Cho ◽

Kyung-Hoae Koo ◽

Pawan Kapur ◽

Krishna C. Saraswat

Keyword(s):

Carbon Nanotube ◽

Global Interconnects ◽

On Chip ◽

Nanotube Bundle ◽

Low K

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Impact of interconnect length changes on effective materials properties (dielectric constant)

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231972 ◽

2007 ◽

Cited By ~ 5

Author(s):

Mary Y. Lanzerotti ◽

Giovanni Fiorenza ◽

Rick A. Rand

Keyword(s):

Dielectric Constant ◽

Materials Properties ◽

Length Changes

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Stochastic interconnect layout sensitivity model

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231959 ◽

2007 ◽

Cited By ~ 4

Author(s):

Payman Zarkesh-Ha ◽

Ken Doniger

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Congestion estimation and localization in fpgas:

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231963 ◽

2007 ◽

Cited By ~ 12

Author(s):

David Yeager ◽

Darius Chiu ◽

Guy Lemieux

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Statistical circuit optimization considering device andinterconnect process variations

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231966 ◽

2007 ◽

Cited By ~ 1

Author(s):

I-Jye Lin ◽

Tsui-Yee Ling ◽

Yao-Wen Chang

Keyword(s):

Process Variations ◽

Circuit Optimization

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Tutorial on congestion prediction

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231961 ◽

2007 ◽

Cited By ~ 4

Author(s):

Taraneh Taghavi ◽

Foad Dabiri ◽

Ani Nahapetian ◽

Majid Sarrafzadeh

Keyword(s):

Congestion Prediction

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An accurate and efficient probabilistic congestion estimation model in x architecture

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231962 ◽

2007 ◽

Cited By ~ 1

Author(s):

Yaoguang Wei ◽

Sheqin Dong ◽

Xianlong Hong ◽

Yuchun Ma

Keyword(s):

Estimation Model ◽

X Architecture

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Principle hessian direction based parameter reduction forinterconnect networks with process variation

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231965 ◽

2007 ◽

Author(s):

Alexander V. Mitev ◽

Michael Marefat ◽

Dongsheng Ma ◽

Janet Wang

Keyword(s):

Process Variation ◽

Parameter Reduction

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Networks on chips

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231968 ◽

2007 ◽

Cited By ~ 2

Author(s):

Avi Kolodny

Keyword(s):

Networks On Chips

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Exploiting on-chip data behavior for delay minimization

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231977 ◽

2007 ◽

Author(s):

Nallamothu Satyanarayana ◽

Madhu Mutyam ◽

A Vinaya Babu

Keyword(s):

Chip Data ◽

Delay Minimization ◽

On Chip

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Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects

Impact of interconnect length changes on effective materials properties (dielectric constant)

Stochastic interconnect layout sensitivity model

Congestion estimation and localization in fpgas:

Statistical circuit optimization considering device andinterconnect process variations

Tutorial on congestion prediction

An accurate and efficient probabilistic congestion estimation model in x architecture

Principle hessian direction based parameter reduction forinterconnect networks with process variation

Networks on chips

Exploiting on-chip data behavior for delay minimization

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07
Latest Publications