Simultaneous Formation of n- and p-Type Ohmic Contacts to 4H-SiC Using the Binary Ni/Al System

2008 ◽  
Vol 1069 ◽  
Author(s):  
Kazuhiro Ito ◽  
Toshitake Onishi ◽  
Hidehisa Takeda ◽  
Susumu Tsukimoto ◽  
Mitsuru Konno ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
High Vacuum ◽  
Contact Layer ◽  
Ultra High Vacuum ◽  
Oxide Semiconductor ◽  
Simultaneous Formation ◽  
Ohmic Behavior ◽  
P Type

ABSTRACTFabrication procedure for silicon carbide power metal oxide semiconductor field effect transistors can be improved through simultaneous formation of ohmic contacts on both the n-source and p-well regions. We have succeeded in the simultaneous formation of Ni/Al ohmic contacts to n- and p-type SiC after annealing at 1000°C for 5 mins in an ultra-high vacuum. Ohmic contacts to n-type SiC were found when Al-layer thickness was less than about 5 nm while ohmic contacts to p-type SiC were observed for an Al-layer thickness greater than about 5 nm. Only the contacts with Al-layer thicknesses in the range of 5 to 6 nm exhibited ohmic behavior to both n- and p-type SiC, with specific contact resistances of 1.8 × 10−4 Ωcm2 and 1.2 × 10−2 Ωcm2 for n- and p-type SiC, respectively. An about 100 nm-thick contact layer was uniformly formed on the SiC substrate and polycrystalline δ-Ni2Si(Al) grains were formed at the contact/SiC interface. The distribution in values for the Al/Ni ratio in the δ-Ni2Si(Al) grains which exhibited ohmic behavior to both n- and p-type SiC was the largest. The smallest average δ-Ni2Si(Al) grain size was also observed in these contacts. Thus, the large distribution in the Al/Ni ratios and a fine microstructure were found to be characteristic of the ohmic contacts to both n- and p-type SiC.

Ti/AlNi/W and Ti/Ni2Si/W Ohmic Contacts to P-Type SiC

2006 ◽  
Vol 527-529 ◽  
pp. 903-906 ◽  
Author(s):  
Bang Hung Tsao ◽  
Jacob Lawson ◽  
James D. Scofield
Keyword(s):  
Ohmic Contacts ◽  
High Vacuum ◽  
Surface Region ◽  
Contact Layer ◽  
Ohmic Behavior ◽  
Specific Contact ◽  
Main Observation ◽  
The Stability ◽  
P Type ◽  
Contact Resistivities

AlNi and Ni2Si based ohmic contacts to p-type 4H-SiC have been produced using low energy ion implantation, a Ti contact layer, and sequential anneals. Low resistivities were promoted by degenerately (>1020 cm-3) doping the surface region of 4H-SiC epilayers via Al+ implantation. High acceptor activation and improved surface morphology was achieved by capping the samples with pyrolized photoresist and using a two-step anneal sequence in argon. Ti/AlNi/W and Ti/Ni2Si/W stacks of varying Ti and/or binary layer thickness were compared at varying anneal temperatures. AlNi based samples reliably and repeatedly achieved specific contact resistivities as low as 5.5 x10-5 ohm-cm2 after annealing at temperatures of 700-1000°C. For the Ni2Si samples, resistivities as low 4.5x10-4 ohm-cm2 were reached after annealing between 750 and 1100°C. Similarly, a set of Ti/AlNi/Au samples, with or without Ge as an additional contact layer, were prepared via the same procedures. In this case, specific contact resistivities as low as 5.0 x10-4 ohm-cm2 were achieved after annealing the Ti/AlNi/Au samples between 600 and 700°C for 30 minutes in a dynamic argon atmosphere or under high vacuum. The lowest resistivities were realized using thicker (~ 40 nm) Ti layers. I-V analysis revealed superior linear characteristics for the AlNi system, which also exhibited a more stable microstructure after anneal. SIMS and RBS were used to analyze the stability of the stacks subsequent to thermal treatment. AFM analysis demonstrated the superiority of photoresist capping over alternatives in minimizing surface roughness. Linear ohmic behavior after significantly reduced anneal temperature is the main observation of the present study.

Simultaneous Formation of Ohmic Contacts for Both N- and P-Type 4H-Sic Using Nial-Based Contact Materials

2006 ◽  
Vol 911 ◽  
Author(s):  
Susumu Tsukimoto ◽  
Toshitake Onishi ◽  
Kazuhiro Ito ◽  
Masanori Murakami
Keyword(s):  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Strong Dependence ◽  
Oxide Semiconductor ◽  
Simultaneous Formation ◽  
Contact Materials ◽  
Specific Contact ◽  
One Step ◽  
Lower Temperature ◽  
P Type

AbstractIn order to simplify a fabrication process of silicon carbide power MOSFETs (metal oxide semiconductor field effect transistors), development of a simultaneous formation process of ohmic contacts to both the p-well and n-source regions of the SiC devices using same contact materials and one step annealing was challenged. We succeeded to develop NiAl-based contact materials which provided ohmic behaviors for both n- and p-type 4H-SiC after one step annealing. The Ni/Al and Ni/Ti/Al ohmic contacts were prepared by depositing sequentially Ni, (Ti) and Al layers with various layer thicknesses onto the n- and p-type SiC substrates which were doped with N at 1 × 1019 cm-3 and with Al at 8 × 1018 cm-3, respectively. The Ni(50 nm)/Al(5 ~ 6 nm) contacts showed ohmic behaviors for both the n- and p-type SiC substrates after annealing at 1000 °C. The Ni(20 nm)/Ti(50 nm)/Al(50 ~ 70 nm) contacts showed ohmic behaviors for both the n- and p-type SiC substrates after annealing at a lower temperature of 800 °C. The specific contact resistances of these contacts were measured to be in the order of 10-3 Ω-cm2 for both p- and n-type SiC, and were found to have strong dependence of the Al layer thicknesses of materials. The interfacial microstructures of the NiAl-based contacts were also observed by transmission electron microscopy (TEM) to understand the current transport mechanism through the metal/SiC interfaces.

Ion Implantation Technique For Simultaneous Formation of A Shallow Silicon p-n Junction and a Shallow Silicide-Silicon Ohmic Contact

1982 ◽  
Vol 18 ◽  
Author(s):  
B.-Y. Tsaur ◽  
C. H. Anderson
Keyword(s):  
Ohmic Contact ◽  
Field Effect Transistors ◽  
Metal Layer ◽  
Electron Beam Evaporation ◽  
Oxide Semiconductor ◽  
Implantation Technique ◽  
Simultaneous Formation ◽  
P Type ◽  
Subsequent Thermal Annealing ◽  
Device Size

Electron beam evaporation is used to coat a p-type silicon substrate with a thin layer of tungsten and then with alternating layers of silicon and tungsten. Bombardment of the coated substrate with As+ ions causes intermixing of the metal and silicon layers, dispersion of contaminant atoms at the interface between the first metal layer and the substrate, and implantation of arsenic atoms in the substrate. Subsequent thermal annealing produces a shallow silicide–silicon ohmic contact and simultaneously activates the implanted arsenic donors to form a shallow p–n+ junction. This technique has been used for the fabrication of mesa diodes with good junction characteristics. A simplified version, in which only a single tungsten layer is deposited on the substrate, has been used as a self–aligned process in the fabrication of metal/oxide/semiconductor field effect transistors with a polycide gate. In the transistors the silicide contacts to the source and drain regions can be made very close to the gate, reducing both the series resistance of these regions and the overall device size.

TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

Impact of Ge Content on Flicker Noise Behavior of Strained-SiGe p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

2009 ◽  
Vol 48 (4) ◽  
pp. 04C036 ◽  
Author(s):  
San-Lein Wu ◽  
Chung Yi Wu ◽  
Hau-Yu Lin ◽  
Cheng-Wen Kuo ◽  
Shin-Hsin Chen ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Flicker Noise ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
P Type ◽  
Strained Sige

Laser cleaning of exfoliated graphene

2012 ◽  
Vol 1455 ◽  
Author(s):  
Oliver Ochedowski ◽  
Benedict Kleine Bußmann ◽  
Marika Schleberger
Keyword(s):  
Local Heating ◽  
High Vacuum ◽  
Ultra High Vacuum ◽  
Ambient Conditions ◽  
Kelvin Probe ◽  
Structural Modifications ◽  
Force Microscopy ◽  
Exfoliated Graphene ◽  
Atomic Force ◽  
P Type

ABSTRACTWe have employed atomic force and Kelvin-Probe force microscopy to study graphene sheets exfoliated on TiO2 under the influence of local heating achieved by laser irradiation. Exfoliation and irradiation took place under ambient conditions, the measurements were performed in ultra high vacuum. We show that after irradiation times of 6 min, an increase of the surface potential is observed which indicates a decrease of p-type carrier concentration. We attribute this effect to the removal of adsorbates like water and oxygen. After irradiation times of 12 min our topography images reveal severe structural modifications of graphene. These resemble the nanocrystallite network which form on graphene/SiO2 but after much longer irradiation times. From our results we propose that short laser heating at moderate powers might offer a way to clean graphene without inducing unwanted structural modifications.

Carbon Incorporation in Gaas grown by UHVCVD Using Trimethylgallium and Arsine

1992 ◽  
Vol 281 ◽  
Author(s):  
Seong-Ju Park ◽  
Jeong-Rae Ro ◽  
Jae-Ki Sim ◽  
El-Hang Lee
Keyword(s):  
Growth Rates ◽  
Hole Concentration ◽  
High Vacuum ◽  
Chemical Vapor ◽  
Ultra High Vacuum ◽  
Chemical Beam Epitaxy ◽  
Hydrogen Atoms ◽  
Carbon Incorporation ◽  
Significant Drop ◽  
P Type

ABSTRACTWe present results of a study on the effect of unprecracked arsine(AsH3) and trimethylgallium(TMGa) on carbon incorporation in UHVCVD(Ultra High Vacuum Chemical Vapor Deposition) grown GaAs epilayers on GaAs(100). Three distinct temperature-dependent regions of growth rates were identified as growth temperature was increased from 570 to 690°C. The growth rates were also strongly dependent on V/III ratio in a range of 5 to 30, which clearly indicates that the growth rate is determined by the amount of arsenic adsorbed on the surface at low V/III ratio and adsorption of TMGa or decomposition process at high V/III ratio. Hall concentration measurements and low temperature photoluminescence data show that the films are all p-type and their impurity concentrations are reduced by two orders of magnitude compared to those of epilayers grown by CBE(Chemical Beam Epitaxy) which employs TMGa and arsenic(precracked arsines) as source materials. Our results indicate that the hydrogen atoms dissociated from adsorbed arsine may remove hydrocarbon species resulting in a significant drop in hole concentration.

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