Wideband transformer-coupled E-band power amplifier in 90 nm CMOS

Author(s):  
Igor Gertman ◽  
Eran Socher

In this work, the design of the wideband millimeter-wave power amplifier for multiband communication is presented. In order to achieve compact, simple and robust design, a differential cascade transformer-coupled topology is used. The amplifier is implemented in 90 nm low-leakage CMOS technology and achieves 3 dB bandwidth of 8 GHz (from 60 to 68 GHz) and a peak gain of 18 dB. The PO1dB is better than 5 dBm from 58 to 80 GHz, and peak output power is 11.9 dBm with 1 dB flatness from 62 to 77 GHz. The chip consumes an area of 0.25 mm2 including bond pads and DC current of 125 mA from a 2.2 V supply.

Author(s):  
Sungah Lee ◽  
Chenglin Cui ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim

2009 ◽  
Vol 1 (2) ◽  
pp. 99-107 ◽  
Author(s):  
Alessandro Cidronali ◽  
Iacopo Magrini ◽  
Niccolò Giovannelli ◽  
Massimiliano Mercanti ◽  
Gianfranco Manes

This paper presents a feasibility study for the implementation of a concurrent dual-band power amplifier (PA) design suitable for 1.98 GHz WCDMA and 3.42 GHz WiMAX digital systems. The proposed PA design was compared with a test bed based on a pair of dedicated single-frequency band PAs. The dual-band PA exhibited simultaneous peak output power levels of 24 and 17 dBm in the lower and in the higher bands to maintain ACPR and EVM requirements below 33 dBc and 5%, respectively. The conclusions drawn in the paper justify the design effort of this innovative solution, which is capable of increasing the PAE for concurrent dual-band operation maintaining the performance of more conventional solutions.


Author(s):  
Uroschanit Yodprasit ◽  
Kosuke Katayama ◽  
Ryuichi Fujimoto ◽  
Mizuki Motoyoshi ◽  
Minoru Fujishima

Author(s):  
Jun-Seong Kim ◽  
Oh-yun Kwon ◽  
Reem Song ◽  
Byung-Sung Kim

2016 ◽  
Vol 11 (2) ◽  
pp. 97-105
Author(s):  
Bernardo Leite ◽  
Eric Kerhervé ◽  
Didier Belot

This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.


2019 ◽  
Vol 29 (3) ◽  
pp. 234-236 ◽  
Author(s):  
Van-Son Trinh ◽  
Hyohyun Nam ◽  
Jung-Dong Park

2020 ◽  
Vol 30 (1) ◽  
pp. 106-108
Author(s):  
Gwangsik Cho ◽  
Jinseok Park ◽  
Songcheol Hong
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