scholarly journals All-printed large-scale integrated circuits based on organic electrochemical transistors

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Peter Andersson Ersman ◽  
Roman Lassnig ◽  
Jan Strandberg ◽  
Deyu Tu ◽  
Vahid Keshmiri ◽  
...  
Keyword(s):  
Internet Of Things ◽  
Integrated Circuits ◽  
Large Scale ◽  
Low Cost ◽  
Digital Signal ◽  
Monolithically Integrated ◽  
Silicon Chips ◽  
Chip Technology ◽  
Interface Devices ◽  
Organic Electrochemical Transistors

Abstract The communication outposts of the emerging Internet of Things are embodied by ordinary items, which desirably include all-printed flexible sensors, actuators, displays and akin organic electronic interface devices in combination with silicon-based digital signal processing and communication technologies. However, hybrid integration of smart electronic labels is partly hampered due to a lack of technology that (de)multiplex signals between silicon chips and printed electronic devices. Here, we report all-printed 4-to-7 decoders and seven-bit shift registers, including over 100 organic electrochemical transistors each, thus minimizing the number of terminals required to drive monolithically integrated all-printed electrochromic displays. These relatively advanced circuits are enabled by a reduction of the transistor footprint, an effort which includes several further developments of materials and screen printing processes. Our findings demonstrate that digital circuits based on organic electrochemical transistors (OECTs) provide a unique bridge between all-printed organic electronics (OEs) and low-cost silicon chip technology for Internet of Things applications.

scholarly journals Rural Online Distance Education based on Content Delivery Network in Beijing

2015 ◽  
Vol 11 (7) ◽  
pp. 29
Author(s):  
Ji-chun Zhao ◽  
Shi-hong Liu ◽  
Jun-feng Zhang
Keyword(s):  
Distance Education ◽  
Large Scale ◽  
Low Cost ◽  
Content Delivery ◽  
Video Data ◽  
Content Delivery Network ◽  
Online Distance Education ◽  
Chip Technology ◽  
Online Distance ◽  
Delivery Network

The paper proposed the research on rural online distance education (RODE) based on the Beijing rural network condition, which aimed at helping farmers to get agricultural technology more effectively and sufficiently. This is the first platform that was applied to large-scale rural distance education, which combined with peer to peer (P2P) and content delivery network (CDN). What’s more, it initiates network video transmission into the RODE platform, which could save 80% of the bandwidth. In addition, MD5 encryption algorithm, content pre-reading technology and data logic chip technology were used to ensure the security of video data. It has the following advantages: easily deployed, highly scalable and low-cost.

Research on Micro-Certificate Based Security System for Internet of Things

2012 ◽  
Vol 263-266 ◽  
pp. 3125-3129
Author(s):  
Li Ping Du ◽  
Ying Li ◽  
Guan Ning Xu ◽  
Fei Duan
Keyword(s):  
Internet Of Things ◽  
Large Scale ◽  
Rapid Development ◽  
Security System ◽  
Security Requirements ◽  
Full Account ◽  
Chip Technology ◽  
Cryptographic Algorithms ◽  
Encryption Decryption ◽  
The Internet Of Things

The rapid development of internet of things puts forward urgent needs for security. The security system must be studied to adapt to the characteristics of the internet of things. The micro- certificate based security system for internet of things takes full account of the security characteristics of things, and uses the symmetric cryptographic algorithms and security chip technology. This security system can meet the security requirements for large-scale sensor’s authentication, signification and encryption/decryption in internet of things, and improve the security performance of internet of things greatly.

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

2018 ◽  
Vol 57 (4) ◽  
pp. 361-375 ◽  
Author(s):  
J Jency Rubia ◽  
GA Sathish Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Large Scale ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Hardware Complexity ◽  
Logarithmic Number System ◽  
Logarithmic Number

The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

scholarly journals Evaluating Awareness and Perception of Botnet Activity within Consumer Internet-of-Things (IoT) Networks

Informatics ◽  
2019 ◽  
Vol 6 (1) ◽  
pp. 8 ◽  
Author(s):  
Christopher McDermott ◽  
John Isaacs ◽  
Andrei Petrovski
Keyword(s):  
Internet Of Things ◽  
Large Scale ◽  
Low Cost ◽  
Security And Privacy ◽  
Smart Devices ◽  
The Internet ◽  
Clear Correlation ◽  
Technical Knowledge ◽  
Home Networks ◽  
Cross Sectional

The growth of the Internet of Things (IoT), and demand for low-cost, easy-to-deploy devices, has led to the production of swathes of insecure Internet-connected devices. Many can be exploited and leveraged to perform large-scale attacks on the Internet, such as those seen by the Mirai botnet. This paper presents a cross-sectional study of how users value and perceive security and privacy in smart devices found within the IoT. It analyzes user requirements from IoT devices, and the importance placed upon security and privacy. An experimental setup was used to assess user ability to detect threats, in the context of technical knowledge and experience. It clearly demonstrated that without any clear signs when an IoT device was infected, it was very difficult for consumers to detect and be situationally aware of threats exploiting home networks. It also demonstrated that without adequate presentation of data to users, there is no clear correlation between level of technical knowledge and ability to detect infected devices.

scholarly journals Enabling Technologies for Effective Deployment of Internet of Things (IoT) Systems

2020 ◽  
Vol 2 (4) ◽  
pp. 21
Author(s):  
Jamil Y. Khan ◽  
Dong Chen ◽  
Oliver Hulin
Keyword(s):  
Internet Of Things ◽  
Network Design ◽  
Network Architecture ◽  
Large Scale ◽  
Ieee 802.15.4 ◽  
Low Cost ◽  
Large Area ◽  
Coverage Area ◽  
Enabling Technologies ◽  
Networking Technologies

The demand for IoT (Internet of Things) systems that encompass cloud computing, the multitude of low power sensing and data collection electronic devices and distributed communications architecture is increasing at an exponential pace. With increasing interests from different industrial, business and social groups, in the near future it will be necessary to support massive deployment of diverse IoT systems in different geographical areas. Large scale deployment of IoT systems will introduce challenging problems for the communication designers, as the networking is one of the key enabling technologies for the IoT systems. Major challenges include cost effective network architecture, support of large area of coverage and diverse QoS (Quality of Service) requirements, reliability, spectrum requirements, energy requirements, and many other related issues. The paper initially reviews different classes of IoT applications and their communication requirements. Following the review, different communications and networking technologies that can potentially support large scale deployment of IoT systems for different industrial, business and social applications are discussed. The paper then concentrates on wireless networking technologies for IoT systems with specific focus on deployment issues. The deployment discussion concentrates on different IoT systems QoS and networking requirements, cost, coverage area and energy supply requirements. We introduce a sustainable low cost heterogeneous network design using short range radio standards such as IEEE 802.15.4/Zigbee, IEEE 802.11/WLAN that can be used to develop a wide area networks to support large number of IoT devices for various applications. Finally the paper makes some general recommendations towards sustainable network design techniques for future IoT systems that can reduce the OPEX and CAPEX requirements.

scholarly journals Design of High-Speed Low Power Computational Blocks for DSP Processors

2021 ◽  
Vol 11 (2) ◽  
pp. 1419-1429
Author(s):  
Alivelu Manga N.
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Digital Signal ◽  
Oxide Semiconductor ◽  
Performance Criteria

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

III-V CMOS technologies on Si platform

2011 ◽  
Vol 1336 ◽  
Author(s):  
M. Takenaka ◽  
S. Takagi
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Film Formation ◽  
High Electron ◽  
High Quality ◽  
Electron Effective Mass ◽  
Monolithically Integrated ◽  
Si Substrates ◽  
Future Technology

ABSTRACTThe heterogeneous integration of III-V semiconductors with the Si platform is expected to provide high performance CMOS logic for future technology nodes because of high electron mobility and low electron effective mass in III-V semiconductors. However, there are many technology issues to be addressed for integrating III-V MOSFETs on the Si platform as follow; high-quality MOS interface formation, low resistivity source/drain formation, and high-quality III-V film formation on Si substrates. In this paper, we present several possible solutions for the above critical issues of III-V MOSFETs on the Si platform. In addition, we present the III-V CMOS photonics platform on which III-V MOSFETs and III-V photonics can be monolithically integrated for ultra-large scale electric-optic integrated circuits.

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