scholarly journals A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation

1998 ◽  
Vol 45 (3) ◽  
pp. 580-589 ◽  
Author(s):  
J.A. Davis ◽  
V.K. De ◽  
J.D. Meindl
Keyword(s):  
Length Distribution ◽  
Wire Length ◽  
Gigascale Integration

Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl
Keyword(s):  
Response Time ◽  
Length Distribution ◽  
Path Model ◽  
System Level ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Logic Network ◽  
Binary Switching ◽  
Quantitative Definition

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

1996 ◽  
Vol 427 ◽  
Author(s):  
Jeffrey A. Davis ◽  
John C. Eble ◽  
Vivek K. De ◽  
James D. Meindl
Keyword(s):  
Empirical Relationship ◽  
Length Distribution ◽  
Gigascale Integration ◽  
Low Dielectric ◽  
Chip Size ◽  
Overall Performance ◽  
Copper Aluminum ◽  
On Chip ◽  
Generic System ◽  
New Distribution

AbstractBased on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution

2004 ◽  
Author(s):  
Takanori Kyogoku ◽  
Junpei Inoue ◽  
Hidenari Nakashima ◽  
Kenichi Okada ◽  
Kazuya Masu
Keyword(s):  
Optimization Technique ◽  
Length Distribution ◽  
Wire Length

Quantitative Derivation and Evaluation of Wire Length Distribution in Three-Dimensional Integrated Circuits Using Simulated Quenching

2006 ◽  
Vol 45 (4B) ◽  
pp. 3260-3265 ◽  
Author(s):  
Jun Deguchi ◽  
Takeaki Sugimura ◽  
Yoshihiro Nakatani ◽  
Takafumi Fukushima ◽  
Mitsumasa Koyanagi
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Length Distribution ◽  
Wire Length
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