Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

Author(s):  
Edouard Bahous ◽  
Ram Srinivasan ◽  
Priyank Saxena ◽  
John Bowen

UV sensors were tested to evaluate the response and reliability as a flameout detection system to reduce system level risks. In this study, UV sensors from two manufacturers were tested on high pressure experimental rigs and on a 15MW gas turbine engine with annular diffusion flame combustion system. Tests were run to investigate the effect of fuel composition, engine load, and sensor circumferential position. The effect of each variable on sensor signal strength and response time is presented in this paper. The response time of the sensor is evaluated against the rate of change of combustor pressure and the time for fuel-air mixture to reach lean extinction limit in the primary zone. Results show that the UV sensor response is not affected by engine load, circumferential location of the sensors, or fuel composition down to Wobbe index of 18.7 MJ/Sm3. At lower Wobbe indices, the signal strength decreased significantly. This result has been attributed to the movement of flame location away from the line of sight of the sensor. Furthermore, it was found that the UV sensor responded before the bulk average reactant mixture reached lean blow out fuel-air ratios. When compared to the baseline detection system the UV sensor performs faster at low load conditions (800 milliseconds) but slower at full load conditions (400 milliseconds). Experimental rig testing led to similar conclusions for sensor response time and signal strength. Future testing of UV sensors on hydrogen blends is planned.


1996 ◽  
Vol 427 ◽  
Author(s):  
Jeffrey A. Davis ◽  
John C. Eble ◽  
Vivek K. De ◽  
James D. Meindl

AbstractBased on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.


2004 ◽  
Author(s):  
Takanori Kyogoku ◽  
Junpei Inoue ◽  
Hidenari Nakashima ◽  
Kenichi Okada ◽  
Kazuya Masu

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