scholarly journals Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic

2017 ◽  
Vol 6 (2) ◽  
pp. 122-132
Author(s):  
Deepika Bansal ◽  
Brahmadeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Performance Improvement ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Charge Sharing ◽  
Domino Logic ◽  
Dynamic Circuits ◽  
Low Power Dissipation ◽  
High System ◽  
Domino Circuits

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

A Novel Low Power Technique for FinFET Domino OR Logic

2020 ◽  
pp. 2150117
Author(s):  
Kajal ◽  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Logic Gates ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Large Power ◽  
Leakage Reduction ◽  
The Impact

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

scholarly journals Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

2020 ◽  
Vol 9 (1) ◽  
pp. 465-473
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Digital Circuit ◽  
Logic Circuits ◽  
Digital Circuit Design ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
In Series ◽  
Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

DYNAMIC GaAs LOGIC CIRCUITS

1991 ◽  
Vol 02 (03) ◽  
pp. 163-183
Author(s):  
DAVID H.K. HOE ◽  
C. ANDRE T. SALAMA
Keyword(s):  
Power Dissipation ◽  
Clock Cycle ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
System Throughput ◽  
Leakage Currents ◽  
Design And Implementation ◽  
Main Challenge ◽  
Dynamic Circuits ◽  
Functional Blocks

Because of their ratioless nature, dynamic logic has several advantages over conventional static techniques used in GaAs . The ability to implement complex gates with dynamic logic leads to circuits with increased speed and reduced power dissipation. Several dynamic configurations using GaAs MESFETs are reviewed. The main challenge is to overcome leakage currents associated with the Schottky gate junctions in order to allow reliable dynamic operation. The pipelining of GaAs dynamic circuits, which allows full use of the clock cycle and improves system throughput, is also discussed. The feasibility of using these dynamic designs in GaAs is illustrated through the design and implementation of complex functional blocks.

Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies

2016 ◽  
Vol 13 (10) ◽  
pp. 6999-7008
Author(s):  
N Anusha ◽  
T Sasilatha
Keyword(s):  
Comparative Analysis ◽  
Performance Analysis ◽  
Metal Oxide ◽  
Leakage Current ◽  
Power Dissipation ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Oxide Semiconductors ◽  
Dynamic Circuits

Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

scholarly journals Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation

2017 ◽  
Vol 7 (5) ◽  
pp. 2468 ◽  
Author(s):  
J. Muralidharan ◽  
P. Manimegalai
Keyword(s):  
Low Power ◽  
Performance Improvement ◽  
High Speed ◽  
Noise Immunity ◽  
Performance Metrics ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Rapid Progression ◽  
Domino Logic ◽  
Rapid Process

The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.

scholarly journals Novel Hybrid SETMOS Logic for Ultra-low-power Applications

2021 ◽  
Author(s):  
Raj Sanjivkumar Shah ◽  
Rutu Parekh ◽  
Rasika Dhavse
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Room Temperature ◽  
Logic Gates ◽  
Logic Circuits ◽  
Total Power ◽  
Ultra Low Power ◽  
Temperature Variations ◽  
Electron Transistors

Abstract This paper investigates the Single-GateSingle Electron Transistors (SG-SETs) based hybrid SETMOS logic circuits for ultra-low-power applications at room temperature. The methodological design of the proposed hybrid SETMOS logic circuits is compatible with 22- nm CMOS bias and process. The widely acclaimed Mahapatra-IonescuBannerjee (MIB) model is modified to implement the proposed SG-SET and hybrid SETMOS logic circuits using Verilog-A. Logic inverter, two-input NAND, NOR, AND, OR, EX-OR, and EX-NOR logic gates are simulated at room temperature using novel SETMOS hybridization. The proposed work is compared with the 22-nm CMOS counterpart (simulated with the same setup). We found that the reduction in total power dissipation by 98.04%, 96.45%, 94.65%, 93.7%, 92.63%, 93.52%, 95.57% using hybrid SETMOS NAND, NOR, AND, EX-OR and EXOR gates than 22 nm CMOS logic gates. The proposed work is compared with other works of literature. We also examined the robustness of the proposed logic circuits against temperature variations from 77 K to 500 K.

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