Extension of EMPSIJ for Estimating the Impact of Substrate Noise on Jitter in a CMOS Inverter

2018 ◽  
Author(s):  
Vijender Kumar Sharma ◽  
Jai Narayan Tripathi ◽  
Hitesh Shrimali
Keyword(s):  
Substrate Noise ◽  
Cmos Inverter ◽  
The Impact

scholarly journals Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2906
Author(s):  
Zahra Abedi ◽  
Sameer Hemmady ◽  
Thomas Antonsen ◽  
Edl Schamiloglu ◽  
Payman Zarkesh-Ha
Keyword(s):  
Predictive Model ◽  
Leakage Current ◽  
Electromagnetic Interference ◽  
High Frequency ◽  
Failure Modes ◽  
Current Model ◽  
Measurement Data ◽  
Logic Gates ◽  
Cmos Inverter ◽  
The Impact

In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers

2013 ◽  
Author(s):  
Marco Cazzaniga ◽  
Patrice Joubert Doriol ◽  
Aurora Sanna ◽  
Emmanuel Blanc ◽  
Valentino Liberali ◽  
...  
Keyword(s):  
Substrate Noise ◽  
The Impact ◽  
Conducted Emi

A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems

2009 ◽  
Vol 28 (11) ◽  
pp. 1613-1626 ◽  
Author(s):  
S. Bronckers ◽  
K. Scheir ◽  
G. Van der Plas ◽  
G. Vandersteen ◽  
Y. Rolain
Keyword(s):  
Substrate Noise ◽  
Rf Systems ◽  
The Impact

scholarly journals Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

2017 ◽  
Author(s):  
Milaim Zabeli ◽  
Nebi Caka ◽  
Myzafere Limani ◽  
Qamil Kabashi
Keyword(s):  
Threshold Voltage ◽  
Logic Circuits ◽  
Physical Parameters ◽  
Design Phase ◽  
Cmos Inverter ◽  
Static Mode ◽  
Operation Conditions ◽  
Mode Of Operation ◽  
The Impact

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.

scholarly journals FinFET Inverter Designs: Behavior and Challenges of Process Variability

2021 ◽  
Vol 16 (2) ◽  
pp. 1-13
Author(s):  
Leonardo Barlette De Moraes ◽  
Alexandra Lackmann Zimpeck ◽  
Cristina Minhardt ◽  
Ricardo Augusto Da Luz Reis
Keyword(s):  
Energy Consumption ◽  
Radiation Effects ◽  
Noise Immunity ◽  
Supply Voltage ◽  
Cost Benefit Analysis ◽  
Schmitt Trigger ◽  
Modern Technology ◽  
Cmos Inverter ◽  
Process Variability ◽  
The Impact

Abstract— Technology scaling alongside the increasing process variability impact in modern technology nodes are themain reasons to control deviations over metrics in IC nanome-ter designs. Schmitt Triggers are traditionally used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and process variability impact. The main contribution of this work is to trace the relationship between transistor sizing, supply voltage, and process variability to get a low energy consumption circuit while still keeping low levels of deviations due to the impact of process-induced variability. It is shown that a cost-benefit analysis can highlight sets of sizing and supply voltage where it can provide a 37.51% decrease in energy consumption while only increasing its sensibility by 7.42%. Furthermore, it is presented that the dependence of supply voltage and sensibility to process variability is not directly related, with slight decreases in the supply volt-ages bringing better results. Overall, the traditional CMOS inverter is still the fastest and most energy-efficient circuit, although, when comparing noise immunity characteristics, the 6-Transistor Schmitt Trigger presents higher noise margins, slopes, gains, and hysteresis ratios. The improvements,although, may increase propagation times, energy consumption, and area.

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