PCB Integrated Inductor Design Optimized and Electrical Performance Analysis for Power Module Development

Author(s):  
Shu-Ting Yang ◽  
Chi-Hao Chiang ◽  
Yu-Chang Hsieh ◽  
Pao-Nan Lee ◽  
Chen-Chao Wang
Author(s):  
Hung-Chun Kuo ◽  
Ming-Fong Jhong ◽  
Hung-Hsiang Cheng ◽  
Chen-Chao Wang ◽  
Chih-Pin Hung

2012 ◽  
Author(s):  
ARINDAM MAITRA ◽  
◽  
RAY LITWIN ◽  
Jason lai ◽  
David Syracuse

Author(s):  
Rafael Vargas-Bernal

Electrical interconnects are essential elements to transmit electrical current and/or to apply electrical voltage to the electronic devices found in an integrated circuit. With the introduction of carbon nanotubes in electronic applications, efficient and high-speed interconnects have allowed for optimizing the electrical performance of the integrated circuits. Additionally, technical problems, such as electromigration, large values of parasitic elements, large delays, and high thermal dissipation, presented in metallic interconnects based on copper, can be avoided. This chapter presents a performance analysis of interconnects used in AMS/RF IC design based on carbon nanotubes as the physical material where electrical variables are provided.


2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000737-000767
Author(s):  
Cyprian Uzoh ◽  
Liang Wang ◽  
Zhuowen Sun ◽  
Andrew Cao ◽  
Bong-Sub Lee ◽  
...  

3D-IC has been increasingly adopted by the industry owing to its promise of higher device speed and package bandwidth, improved power consumption, reduced form factor, and lower cost for important applications over a wide range of industrial segments including image sensors, logic-memory and logic-logic integration, MEMS, integrated optical interposers and LEDs. This presentation is a systematic study of multiple experimental factors affecting the electrical performance, reliability and scalability of TSVs. Electrical modeling and simulation was used to determine the key factors influencing singal transmission and return losses in TSVs at high (>1 GHz) frequencies. A variety of process modules and steps for the fabrication of through silicon vias were then systematically optimized to ensure high performance. The modules evaluated include TSV etch, TSV fill, chemical mechanical polishing (CMP), pad finish, bonding schemes, wafer thinning, via reveal, passivation, wiring and bumping. One example is the improvement of TSV profile and sidewall roughness through the optimization of DRIE parameters and wet chemical methods to reduce silicon sidewall roughness from that of a typical Bosch etch to less than 10nm which is critical for adhesion of barrier/seed layer and the final reliability of 2.5D packaging. Scalability of void-free via fill process with respect to TSV diameter and depth was addressed by using highly conformal barrier layers. Adhesion of Cu to the barrier layer was also improved upon detailed analysis to prevent delamination and improve reliability. A bottom up plating chemistry with significantly low impurity content was utilized to mitigate voids, seams and excessive overburden in the TSV. Its impact on stress and delamination issues and subsequent reliability failures was studied in details. The annealing process following TSV formation is systematically studied with varying conditions and characterized with metrology and electrical tests to investigate its effect on microstructure and material properties. The process parameters were tuned for CMP of Cu, adhesion and barrier layer without causing corrosion or delamination between adjacent layers. Process requirements for these modules in TSV process are closely related. This presentation will review the process module development in the context of their effects on the integrated TSV parameters (performance, reliability and scalability). We will also provide an in-depth discussion on process module optimization, electrical and mechanical characterization and cost reduction methodologies.


2017 ◽  
Vol 2017 (1) ◽  
pp. 000353-000359
Author(s):  
Xin Zhao ◽  
K. Jagannadham ◽  
Douglas C. Hopkins

Abstract Wide Bandgap (WBG) power devices have become the most promising solution for power conversion systems, with the best trade-off between theoretical characteristics, real commercial availability and maturity of fabrications. Advanced packaging technology is being heavily developed to take full advantages of WBG devices, in terms of materials, mechanical design, fabrication and electrical performance optimizations. In this paper, a flexible substrate based 1.2kV SiC Half Bridge Intelligent Power Module with stacked dies is introduced. The module design is based on the concept “Power Supply in Package (PSiP)”, high functionality is integrated in the module. Together with power stages, gate driver circuits, Low Dropout Regulators (LDO), digital isolators, and bootstrap circuits are integrated in the module. An ultra-thin flexible epoxy-resin based dielectric is applied in the module as substrates, its thickness can be as low as 80μm, with 8W/mK thermal conductivity. The SiC switches are double-side solderable, with copper as topside metallization on pads. No bonding wires are applied in the SiC PSiP module. The highside and lowside SiC switches on the phase leg is stacked vertically for interconnections with low parasitic and high denstiy. This work mainly addresses performance evaluation of the PSiP SiC half bridge module by multiphysics simulations. Q3D is employed to evaluate the parasitic inductance and resistance in the module, showing that parasitic inductance is lower than 1.5nH in the design. The extracted parasitics is imported in spice circuit model, simulation results show limited ringing during switching transients. Thermal simulations are employed to compare junction temperature of power modules with DBC subtrates and flexible substrates, then to evaluate the thermal performance of the designed PSiP SiC model with stacked dies. It shows that junction temperature of designed IPM is higher than regular module at same condition. The paper also provides guideline for optimized heat sink design to lower junction temperature of the SiC IPM. Mechanical simulations are employed to evaluate the pre-stress induced in modules with DBC substrate and flexible dielectric substrate, and proves that mechanical stress induced by reflowing process can be reduced significantly by using ultra-thin flexible dielectric as substrate.


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