Automatic Wire-Routing of SFQ Digital Circuits Considering Wire-Length Matching

2016 ◽  
Vol 26 (3) ◽  
pp. 1-5 ◽  
Author(s):  
Nobutaka Kito ◽  
Kazuyoshi Takagi ◽  
Naofumi Takagi
Keyword(s):  
Digital Circuits ◽  
Wire Length ◽  
Wire Routing ◽  
Automatic Wire

DRAWING WITH FAT EDGES

2006 ◽  
Vol 17 (05) ◽  
pp. 1143-1163 ◽  
Author(s):  
CHRISTIAN A. DUNCAN ◽  
ALON EFRAT ◽  
STEPHEN KOBOUROV ◽  
CAROLA WENK
Keyword(s):  
Planar Graphs ◽  
Graph Drawing ◽  
Vlsi Design ◽  
Polynomial Time Algorithm ◽  
Time Algorithm ◽  
Wire Length ◽  
Restricted Class ◽  
Additional Information ◽  
Wire Routing ◽  
Unit Edge

Traditionally, graph drawing algorithms represent vertices as circles and edges as curves connecting the vertices. We introduce the problem of drawing with "fat" edges, i.e., with edges of variable thickness. The thickness of an edge is often used as a visualization cue, to indicate importance, or to convey some additional information. We present a model for drawing with fat edges and a corresponding efficient polynomial time algorithm that uses the model. We first focus on a restricted class of graphs that occur in VLSI wire routing and then show how to extend the algorithm to general planar graphs. We show how to convert an arbitrary wire routing into a homotopically equivalent routing that maximizes the distance between any two wires, which is a desired property in VLSI design. Among such, we obtain the routing with minimum total wire length. A homotopically equivalent routing that maximizes the distance between any two wires yields a graph drawing which maximizes edge thickness. Our algorithm does not require unit edge thickness but can be applied as well in the presence of different edge weights.

ALL-OPTICAL DIGITAL CIRCUITS

1988 ◽  
Vol 49 (C2) ◽  
pp. C2-459-C2-462 ◽  
Author(s):  
F. A.P. TOOLEY ◽  
B. S. WHERRETT ◽  
N. C. CRAFT ◽  
M. R. TAGHIZADEH ◽  
J. F. SNOWDON ◽  
...  
Keyword(s):  
Digital Circuits ◽  
All Optical

Interconnect Limits on Gigascale Integration (GSI)

1997 ◽  
Vol 473 ◽  
Author(s):  
J. A. Davis ◽  
J. D. Meindl
Keyword(s):  
Response Time ◽  
Length Distribution ◽  
Path Model ◽  
System Level ◽  
Wire Length ◽  
Clock Frequency ◽  
Gigascale Integration ◽  
Logic Network ◽  
Binary Switching ◽  
Quantitative Definition

ABSTRACTOpportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, τ, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, τ, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus τ displays requires an estimate of the complete stochastic wiring distribution of a chip.Based on Rent's Rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits with the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distribution for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

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