Bias Annealing of Radiation and Bias Induced Positive Charges in N- and P-Type MOS Capacitors

1985 ◽  
Vol 32 (6) ◽  
pp. 3911-3915 ◽  
Author(s):  
Kazumichi Suzuki ◽  
Masaharu Sakagami ◽  
Eiichi Nishimura ◽  
Kikuo Watanabe
Keyword(s):  
Mos Capacitors ◽  
P Type

Characteristics of MOS Capacitors Formed on p-Type InSb

1974 ◽  
Vol 24 (2) ◽  
pp. 649-652 ◽  
Author(s):  
M. L. Korwin-Pawlowski ◽  
E. L. Heasell
Keyword(s):  
Mos Capacitors ◽  
P Type

scholarly journals Study of p-type silicon MOS capacitors at HL-LHC radiation levels through irradiation with a cobalt-60 gamma source and a TCAD simulation

2021 ◽  
Vol 16 (06) ◽  
pp. P06040
Author(s):  
P. Asenov ◽  
P. Assiouras ◽  
A. Boziari ◽  
K. Filippou ◽  
I. Kazas ◽  
...  
Keyword(s):  
Gamma Source ◽  
Mos Capacitors ◽  
Type Silicon ◽  
Tcad Simulation ◽  
P Type

Influence of various NO annealing conditions on N-type and P-type 4H-SiC MOS capacitors

2019 ◽  
Vol 30 (11) ◽  
pp. 10302-10310
Author(s):  
Yifan Jia ◽  
Hongliang Lv ◽  
Xiaoyan Tang ◽  
Chao Han ◽  
Qingwen Song ◽  
...  
Keyword(s):  
Mos Capacitors ◽  
Annealing Conditions ◽  
P Type

Direct observation of inversion capacitance in p-type diamond MOS capacitors with an electron injection layer

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FR01 ◽  
Author(s):  
Tsubasa Matsumoto ◽  
Hiromitsu Kato ◽  
Toshiharu Makino ◽  
Masahiko Ogura ◽  
Daisuke Takeuchi ◽  
...  
Keyword(s):  
Direct Observation ◽  
Electron Injection ◽  
Mos Capacitors ◽  
Electron Injection Layer ◽  
P Type

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

Comparison of Electrical Behavior of GaN-Based MOS Structures Obtained by Different PECVD Process

2012 ◽  
Vol 711 ◽  
pp. 228-232
Author(s):  
Elias Al Alam ◽  
Ignasi Cortés ◽  
T. Begou ◽  
Antoine Goullet ◽  
Frederique Morancho ◽  
...  
Keyword(s):  
Surface Preparation ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Plasma Oxidation ◽  
Interface Quality ◽  
Mos Capacitors ◽  
Dielectric Thin Film ◽  
P Type ◽  
Mos Structures ◽  
Uv Ozone

MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuousICPPECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

scholarly journals Characterization of epitaxial GaAs MOS capacitors using atomic layer-deposited TiO2/Al2O3 gate stack: study of Ge auto-doping and p-type Zn doping

2012 ◽  
Vol 7 (1) ◽  
Author(s):  
Goutam Kumar Dalapati ◽  
Terence Kin Shun Wong ◽  
Yang Li ◽  
Ching Kean Chia ◽  
Anindita Das ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Gate Stack ◽  
Mos Capacitors ◽  
Zn Doping ◽  
Epitaxial Gaas ◽  
P Type

scholarly journals TCAD Modeling of Surface Radiation Damage Effects: A State-Of-The-Art Review

2021 ◽  
Vol 9 ◽  
Author(s):  
Arianna Morozzi ◽  
Francesco Moscatelli ◽  
Tommaso Croci ◽  
Daniele Passeri
Keyword(s):  
State Of The Art ◽  
Surface Damage ◽  
Surface Radiation ◽  
Particle Detectors ◽  
Mos Capacitors ◽  
X Ray ◽  
Silicon Sensors ◽  
Before And After ◽  
Technology Cad ◽  
P Type

A comprehensive numerical model which accounts for surface damage effects induced by radiation on silicon particle detectors is presented with reference to the state-of-the-art Synopsys Sentaurus Technology CAD (TCAD) tool. The overall aim of this work is to present the “Perugia 2019 Surface” damage modeling scheme, fully implemented within the TCAD environment, which effectively describes the surface damage effects induced by radiation in silicon sensors relying on a limited number of parameters relevant for physics. To this end, extensive measurement campaigns have been recently performed on gated-diodes and MOS capacitors at Fondazione Bruno Kessler (FBK) in Italy, Hamamatsu Photonics (HPK) in Japan and Infineon Technologies (IFX) in Austria on both n-type and p-type substrates (with and without p-spray isolation implants), in order to extrapolate the relevant parameters which rule the surface damage effects. The integrated interface trap density and the oxide charge density, have been determined before and after X-ray irradiation with doses ranging from 0.05 to 100 Mrad(SiO2), for each specific foundry and technology flavor. The main guidelines of this study are the versatility and generality of the simulation approach.

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