A 2.9 mm2 Highly Integrated Low Noise GPS Receiver in 0.18-μm CMOS Technology

2015 ◽  
Vol 24 (03) ◽  
pp. 1550036 ◽  
Author(s):  
Zhengfei Hu ◽  
Li Zhang ◽  
Mindi Huang
Keyword(s):  
Frequency Synthesizer ◽  
Dynamic Range ◽  
Noise Figure ◽  
Gain Control ◽  
Cmos Technology ◽  
Low Noise ◽  
Band Pass Filter ◽  
Gps Receiver ◽  
Voltage Reference ◽  
Pass Filter

An L1 band highly integrated low noise GPS receiver in 0.18-μm CMOS is presented in this paper. The receiver adopts double conversion structure and two dynamic range control modes of variable gain amplifier (VGA) and programmable gain amplifier (PGA). The receiver includes the blocks of LNA, down-conversion mixers, band pass filter, received signal strength indicator (RSSI), VGA, PGA, 2-bit ADC, two frequency synthesizers and so on. The LNA adopts source inductive degeneration technique to achieve good noise performance, and a novel positive feedback capacitor is introduced to enhance gain. The novel gain-boosting charge pump (CP) structure acquires accurate current matching of 0.1% error which improves the output phase noise of frequency synthesizer. The measured radio performances of noise figure (NF) is only 4 dB and the maximum gain is 110 dB. The gain control range achieves 50 dB provided by PGA and VGA. The receiver occupies an area of 1.875 mm × 1.575 mm including all needed voltage reference and the 1.8 V low dropout regulator.

scholarly journals A Low-Voltage Multi-Band ZigBee Transceiver

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1474
Author(s):  
Zhiqun Li ◽  
Yan Yao ◽  
Zengqi Wang ◽  
Guoxiao Cheng ◽  
Lei Luo
Keyword(s):  
Frequency Synthesizer ◽  
Low Voltage ◽  
Supply Voltage ◽  
Maximum Output Power ◽  
Cmos Technology ◽  
Maximum Output ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Front End ◽  
Band Pass

This paper presents a low-voltage ZigBee transceiver covering a unique frequency band of 780/868/915/2400 MHz in 180 nm CMOS technology. The design consists of a receiver with a wideband variable-gain front end and a complex band-pass filter (CBPF) based on poles construction, a transmitter employing the two-point direct-modulation structure, a Ʃ-Δ fractional-N frequency synthesizer with two VCOs and some auxiliary circuits. The measured results show that under 1 V supply voltage, the receiver reaches −93.8 dBm and −102 dBm sensitivity for 2.4 GHz and sub-GHz band, respectively, and dissipates only 1.42 mW power. The frequency synthesizer achieves −106.8 dBc/Hz and −116.7 dBc/Hz phase noise at 1 MHz frequency offset along with 4.2 mW and 3.5 mW power consumption for 2.4 GHz and sub-GHz band, respectively. The transmitter features 2.67 dBm and 12.65 dBm maximum output power at the expense of 21.2 mW and 69.5 mW power for 2.4 GHz and sub-GHz band, respectively.

Performance of a Ferroelectric Tunable Pre-Select Filter/Low Noise Amplifier Hybrid Circuit

1999 ◽  
Vol 603 ◽  
Author(s):  
Guru Subramanyam ◽  
Felix A. Miranda ◽  
Robert R. Romanofsky ◽  
Fred Van Keuls ◽  
Chonglin Chen
Keyword(s):  
Strontium Titanate ◽  
Communication Systems ◽  
Satellite Communication ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Noise Amplifier ◽  
Hybrid Circuit

AbstractIn this paper we discuss the performance of a proof-of-concept of a tunable band pass filter (BPF)/Low Noise Amplifier (LNA) hybrid circuit for a possible gain-compensated down-converter targeted for the next generation of K-band satellite communication systems. Electrical tunability of the filter is obtained through the nonlinear electric field dependence of the relative dielectric constant of a ferroelectric thin-film such as strontium titanate (SrTiO3) or barium strontium titanate (BaxSr1−xTiO3). Experimental results show that the BPFs are tunable by more than 5%, with a bipolar biasing scheme employed. The BPF/LNA tunable hybrid circuit was used to study the effect of tuning on the hybrid circuit's performance especially on the amplifier's noise-figure and the gain.

scholarly journals Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection

VLSI Design ◽  
2015 ◽  
Vol 2015 ◽  
pp. 1-9
Author(s):  
Jian Chen ◽  
Chien-In Henry Chen
Keyword(s):  
Noise Figure ◽  
Process Variation ◽  
Low Noise ◽  
Maximum Deviation ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Average Maximum ◽  
Band Pass ◽  
Tuning Frequency ◽  
High Rejection

A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (<6 dB) provides a wide tuning frequency span (1–2.04 GHz) to accept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness of the BPF after calibration from process variations, operating in 1.04 GHz tuning frequency span: almost zero deviation on center frequency, an average maximum deviation 1.16 dB on a nominal pass band gain of 55.6 dB, and an average maximum deviation 1.06 MHz on a nominal bandwidth of 12.3 MHz.

A WIDEBAND CMOS CASCADED VARIABLE GAIN AMPLIFIER USING UNEQUALLY DISTRIBUTED GAIN CONTROL FOR DVB-S.2 RECEIVER

2013 ◽  
Vol 22 (09) ◽  
pp. 1340008 ◽  
Author(s):  
HYEONSEOK HWANG ◽  
HOONKI KIM ◽  
CHAN-HUI JEONG ◽  
CHAN-KEUN KWON ◽  
SANGGEUN JEON ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
Gain Control ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Control Voltage ◽  
Current Generation ◽  
Fully Integrated ◽  
Variable Gain ◽  
Current Converter

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

scholarly journals Methods of structural and functional implementation of ultra-wide range receiving paths

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (7) ◽  
pp. 23-30
Author(s):  
D. V. Arkhipenkov ◽  
I. I. Zabenkov ◽  
S. S. Salanovich
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
Low Noise ◽  
Radio Receiver ◽  
Monitoring Systems ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Radio Monitoring ◽  
Wide Range ◽  
Element Base

Currently, radio monitoring systems are being actively improved in the direction of expanding the range of operating frequencies and the width of the spectrum of processed signals, which in some cases requires changing approaches to the design of their receiving devices. The purpose of the article is to substantiate the methods and circuit design options for implementing a receiver of an ultra-wide-range radio monitoring system and to justify the sequence of selecting the element base and calculating the parameters of the receiving path. The research proves expedient to choose the infradine structure of the radio receiving path as a basis, in which the frequency of the mirror channel is located far from the frequency of the main channel, so the mirror channel is easily suppressed by a simple low-pass filter. One of the main problems that arise when designing ultra-wideband radio receivers is the simultaneous provision of a large dynamic range and a low noise figure. To reduce the noise figure, a variant of constructing a path was proposed, starting with a low-noise amplifier with increased parameters of nonlinear selectivity, which is acceptable if there is a low probability of intermodulation combinations. The article suggests a receiver with an operating frequency range of 0.5–18 GHz and an analogto-digital converter with a speed of up to 10.4 GSPS. The element base was selected for the receiving devices and the main parameters of the path were calculated. A number of examples are used to analyze the ways to increase the dynamic range of a radio receiver and the influence of element base parameters on the device performance. The main technical characteristics of the radio receiver for effective operation of modern radio monitoring systems and the ways to increase the dynamic range thereof are described.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

Sign in / Sign up

Export Citation Format

Share Document