Failure Analysis of Discolored Bondpads in Wafer Fabrication

1999 ◽  
Author(s):  
Younan N. Hua
Keyword(s):  
Failure Analysis ◽  
Surface Analysis ◽  
Trace Amount ◽  
Wafer Fabrication ◽  
Al Alloy ◽  
Wafer Fab ◽  
Analysis Technique ◽  
Pull Testing ◽  
Etch Time

Abstract Discolored bondpads & non-stick failure in 0.6 μm wafer fab process with the hot Al alloy metallization was investigated. SEM, EDX & AES techniques were used to identify the root causes. Failure analysis results showed that discolored bondpads & non-stick failure were caused by TiN residue introduced during L95 bondpad opening wafer fab process. TiN residue on bondpad might have led to non-stick bondpad issue. The results also showed that it was difficult to determine the trace amount of TiN residue on bondpad using EDX technique due to its limitations. In this work, Auger surface analysis technique was used to determine TiN residue on bondpads with Al/TiW/Ti metallization. Auger results showed that Ti & N peaks were detected on discolored bondpads. It has resulted in non-stick bondpad failure. The solution to eliminate TiN residue on bondpads was to increase etch time at L95 bondpad opening wafer fab process. After using the new recipe with longer etch time, Auger results on the bondpads showed that no Ti & N peaks were detected and the bond-pull testing also passed.

Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing

2000 ◽  
Author(s):  
Y. N. Hua ◽  
E. C. Low ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Failure Analysis ◽  
Feed Rate ◽  
Galvanic Corrosion ◽  
Experimental Results ◽  
Metal Corrosion ◽  
Wafer Fabrication ◽  
Al Alloy ◽  
Assembly Process ◽  
Water Problem ◽  
Sawing Process

Abstract In our previous paper [1], discolored bondpads due to galvanic corrosion were studied. The results showed that the galvanic corrosion occurred in 0.8 ìm wafer fabrication (fab) process with cold Al alloy (Al-Si, 0.8 wt%-Cu, 0.5 wt%) metallization. Galvanic corrosion is also known as a two-metal corrosion and it could be due to either wafer fab process or assembly process. Our initial suspicion was that it was due to a DI water problem during wafer sawing at assembly process. After that, we did further failure analysis and investigation work on galvanic corrosion of bondpads and further found that galvanic corrosion might be due to longer rinsing time of DI water during wafer sawing. The rinsing time of DI water is related to the cutting time of wafer sawing. Therefore, some experiments of wafer sawing process were done by using different sizes of wafer (1/8 of wafer, a quadrant of wafer and whole of wafer) and different sawing speed (feed-rate). The results showed that if the cutting time was longer than 25 minutes, galvanic corrosion occurred on bondpads. However, if the cutting time was shorter than 25 minutes, galvanic corrosion was eliminated. Based on the experimental results, it is concluded that in order to prevent galvanic corrosion of bondpads, it is necessary to select higher feed-rate during wafer sawing process at assembly houses. In this paper, we will report the details of failure analysis and simulation experimental results, including the solution to eliminate galvanic corrosion of bondpads during wafer sawing at assembly houses.

Studies on Fingerprints of EDX, FTIR, XPS and TOF-SIMS Techniques and Applications in Failure Analysis of Wafer Fabrication

2004 ◽  
Author(s):  
Hua Younan ◽  
Lo Keng Foo ◽  
N. Ramesh Rao ◽  
Z. Q. Mo
Keyword(s):  
Failure Analysis ◽  
Functional Group ◽  
Complex Compounds ◽  
Ftir Spectra ◽  
The Other ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Wafer Fab ◽  
Ftir Technique

Abstract In failure analysis of wafer fabrication it is difficult to identify possible sources of carbon-related contaminants as most of them are from polymers, organic and complex compounds. In this paper, the fingerprints of EDX, FTIR, XPS and TOFSIMS techniques will be introduced so as to identify sources of carbon-related contaminants. For example, Si peak (1.740 keV) can be used as a fingerprint of EDX technique to identify the ink-related contaminant from the other carbon-related contaminants. FTIR spectra of more than 10 possible materials from wafer fab and assembly processes are discussed, which may be used as the fingerprints of FTIR technique to identify carbon-related contaminants. The C=O functional group and the PDMS (PolyDimethylSiloxane) are recommended as the fingerprints of XPS and TOF-SIMS techniques to identify source of carbon-related contaminants, respectively. In this paper, some application cases will be also discussed.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Studies on Chemical Methods to Expose Gate/Tunnel Oxide and Identification of Gate/Tunnel Oxide Defects in Wafer Fabrication

2002 ◽  
Author(s):  
Y. N. Hua ◽  
G. B. Ang ◽  
S. Redkar ◽  
Yogaspari ◽  
Wilma Richter
Keyword(s):  
Acetic Acid ◽  
Silicon Oxide ◽  
Wafer Fabrication ◽  
Chemical Methods ◽  
Advantages And Disadvantages ◽  
Different Types ◽  
Capacitor Structure ◽  
Oxide Defects ◽  
Buffer Oxide Etchant ◽  
Etch Time

Abstract In failure analysis of wafer fabrication, currently, three different types of chemical methods including 6:6:1 (Acetic Acid/HNO3/HF), NaOH and Choline are used in removing polysilicon (poly) layer and exposing the gate/tunnel oxide underneath. However, usage is limited due to their disadvantages. For example, 6:6:1 is a relatively fast etchant, but it is difficult to control the etch time and keep the oxide layer intact. Also, while using NaOH to remove poly and expose the silicon oxide, the solution needs to be heated. It is also difficult to etch a poly layer with a WSix or a CoSix silicide using NaOH. In this paper, we will discuss these 3 etchants in terms of their advantages and disadvantages. We will then introduce a new poly etchant, called HB91. HB91 is useful for removing poly to expose the gate/tunnel oxide for identification of related defects. HB91 is actually a mixture of two chemicals namely nitric acid (HNO3) and buffer oxide etchant (BOE) in a 9:1 ratio. The experimental results show that it is highly selective in poly removal with respect to the gate/tunnel oxide and is a suitable poly etchant especially for removing polysilicon with/without WSix and CoSix in the large capacitor structure. Application results of this poly etchant (HB91) will be presented.

Studies on a Failure Analysis Flow of Surface Contamination, Corrosion, and Underetch on Microchip Al Bondpads in Wafer Fabrication

2005 ◽  
Author(s):  
Hua Younan
Keyword(s):  
Failure Analysis ◽  
Galvanic Corrosion ◽  
Surface Contamination ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Corrosion Passivation

Abstract A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Test Circuit Conditioning for Soft Defect Localization

2014 ◽  
Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich
Keyword(s):  
Laser Beam ◽  
Failure Analysis ◽  
Signal Frequency ◽  
Dynamic Failure ◽  
The Third ◽  
Analysis Technique ◽  
Test Circuit ◽  
Defect Localization ◽  
Manual Input ◽  
Fast Dynamic

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Failure analysis of H13 steel die for high pressure die casting Al alloy

2021 ◽  
pp. 105330
Author(s):  
Rengen Ding ◽  
Haibo Yang ◽  
Shuzhi Li ◽  
Guodong Wu ◽  
Jiahao Mo ◽  
...  
Keyword(s):  
High Pressure ◽  
Failure Analysis ◽  
Die Casting ◽  
Al Alloy ◽  
H13 Steel ◽  
High Pressure Die Casting ◽  
Pressure Die Casting
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