scholarly journals Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

2020 ◽  
Vol 10 (3) ◽  
pp. 28
Author(s):  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Logic Gates ◽  
Expressive Power ◽  
Boolean Logic ◽  
Majority Gate ◽  
Von Neumann ◽  
Majority Logic ◽  
Memory Array ◽  
Memory Wall ◽  
Parallel Prefix

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

scholarly journals Design of In-Memory Parallel-Prefix Adders

2021 ◽  
Vol 11 (4) ◽  
pp. 45
Author(s):  
John Reuben
Keyword(s):  
Computer Arithmetic ◽  
Boolean Logic ◽  
Von Neumann ◽  
Majority Logic ◽  
Memory Array ◽  
Emerging Memory ◽  
Non Volatile Memory ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

scholarly journals Binary Addition in Resistance Switching Memory Array by Sensing Majority

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 496 ◽  
Author(s):  
John Reuben
Keyword(s):  
Energy Efficient ◽  
Full Adder ◽  
Resistance Switching ◽  
Boolean Logic ◽  
Majority Gate ◽  
Efficient Manner ◽  
Computing Systems ◽  
Von Neumann ◽  
Memory Array ◽  
Memory Wall

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.

scholarly journals Digital logic gates in soft, conductive mechanical metamaterials

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Charles El Helou ◽  
Philip R. Buskohl ◽  
Christopher E. Tabor ◽  
Ryan L. Harne
Keyword(s):  
Integrated Circuits ◽  
Electronic Materials ◽  
Polymer Networks ◽  
Conductive Polymer ◽  
Network Connectivity ◽  
Logic Gates ◽  
Boolean Logic ◽  
Digital Logic ◽  
Mechanical Metamaterials ◽  
Logic Operations

AbstractIntegrated circuits utilize networked logic gates to compute Boolean logic operations that are the foundation of modern computation and electronics. With the emergence of flexible electronic materials and devices, an opportunity exists to formulate digital logic from compliant, conductive materials. Here, we introduce a general method of leveraging cellular, mechanical metamaterials composed of conductive polymers to realize all digital logic gates and gate assemblies. We establish a method for applying conductive polymer networks to metamaterial constituents and correlate mechanical buckling modes with network connectivity. With this foundation, each of the conventional logic gates is realized in an equivalent mechanical metamaterial, leading to soft, conductive matter that thinks about applied mechanical stress. These findings may advance the growing fields of soft robotics and smart mechanical matter, and may be leveraged across length scales and physics.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

scholarly journals INFINITARY PROPOSITIONAL RELEVANT LANGUAGES WITH ABSURDITY

2017 ◽  
Vol 10 (4) ◽  
pp. 663-681
Author(s):  
GUILLERMO BADIA
Keyword(s):  
Expressive Power ◽  
Interpolation Theorem ◽  
Boolean Logic ◽  
Isomorphism Theorem ◽  
Strong Completeness ◽  
Lack Of Compactness ◽  
Relevant Logics ◽  
Beth Definability ◽  
Beth Definability Property

AbstractAnalogues of Scott’s isomorphism theorem, Karp’s theorem as well as results on lack of compactness and strong completeness are established for infinitary propositional relevant logics. An “interpolation theorem” (of a particular sort introduced by Barwise and van Benthem) for the infinitary quantificational boolean logic L∞ω holds. This yields a preservation result characterizing the expressive power of infinitary relevant languages with absurdity using the model-theoretic relation of relevant directed bisimulation as well as a Beth definability property.

Reconfigurable nonvolatile boolean logic with one-transistor-two-memristor for in-memory computing

2021 ◽  
Author(s):  
Ziling Wang ◽  
Li Luo ◽  
Jie Li ◽  
Lidan Wang ◽  
shukai duan
Keyword(s):  
Large Scale ◽  
Full Adder ◽  
Boolean Logic ◽  
Device Structure ◽  
Von Neumann ◽  
Computing Paradigm ◽  
Operation Process ◽  
Strong Candidate ◽  
High Flexibility ◽  
Logic Functions

Abstract In-memory computing is highly expected to break the von Neumann bottleneck and memory wall. Memristor with inherent nonvolatile property is considered to be a strong candidate to execute this new computing paradigm. In this work, we have presented a reconfigurable nonvolatile logic method based on one-transistor-two-memristor (1T2M) device structure, inhibiting the sneak path in the large-scale crossbar array. By merely adjusting the applied voltage signals, all 16 binary Boolean logic functions can be achieved in a single cell. More complex computing tasks including one-bit parallel full adder and Set-Reset latch have also been realized with optimization, showing simple operation process, high flexibility, and low computational complexity. The circuit verification based on cadence PSpice simulation is also provided, proving the feasibility of the proposed design. The work in this paper is intended to make progress in constructing architectures for in-memory computing paradigm.

scholarly journals Targeting Acute Myeloid Leukemia Using the RevCAR Platform: A Programmable, Switchable and Combinatorial Strategy

Cancers ◽  
2021 ◽  
Vol 13 (19) ◽  
pp. 4785
Author(s):  
Enrico Kittel-Boselli ◽  
Karla Elizabeth González Soto ◽  
Liliana Rodrigues Loureiro ◽  
Anja Hoffmann ◽  
Ralf Bergmann ◽  
...  
Keyword(s):  
T Cells ◽  
Acute Myeloid Leukemia ◽  
Myeloid Leukemia ◽  
Immune Escape ◽  
Early Stage ◽  
Logic Gates ◽  
Boolean Logic ◽  
In Vivo Models ◽  
Peptide Epitope ◽  
Acute Myeloid

Clinical translation of novel immunotherapeutic strategies such as chimeric antigen receptor (CAR) T-cells in acute myeloid leukemia (AML) is still at an early stage. Major challenges include immune escape and disease relapse demanding for further improvements in CAR design. To overcome such hurdles, we have invented the switchable, flexible and programmable adaptor Reverse (Rev) CAR platform. This consists of T-cells engineered with RevCARs that are primarily inactive as they express an extracellular short peptide epitope incapable of recognizing surface antigens. RevCAR T-cells can be redirected to tumor antigens and controlled by bispecific antibodies cross-linking RevCAR T- and tumor cells resulting in tumor lysis. Remarkably, the RevCAR platform enables combinatorial tumor targeting following Boolean logic gates. We herein show for the first time the applicability of the RevCAR platform to target myeloid malignancies like AML. Applying in vitro and in vivo models, we have proven that AML cell lines as well as patient-derived AML blasts were efficiently killed by redirected RevCAR T-cells targeting CD33 and CD123 in a flexible manner. Furthermore, by targeting both antigens, a Boolean AND gate logic targeting could be achieved using the RevCAR platform. These accomplishments pave the way towards an improved and personalized immunotherapy for AML patients.

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