scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

scholarly journals Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

2021 ◽  
Author(s):  
Mateus B. Castro ◽  
Raphael R. N. Souza ◽  
Agord M. P. Junior ◽  
Eduardo R. Lima ◽  
Leandro T. Manera
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Phase Locked Loop ◽  
Analog To Digital Converters ◽  
Cmos Process ◽  
Reference Frequency ◽  
Process Technology ◽  
Worst Case ◽  
Sigma Delta ◽  
Analog To Digital

AbstractThis paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthesizer generates clock frequencies ranging from 40 to 230 MHz considering a reference frequency of 10 MHz and a supply voltage of 1.2 V. Worst case current consumption is 634 $$\mu $$ μ W, settling time is 6 $$\mu $$ μ s, maximum jitter is 1.3 ns in a 0.037 mm$$^2$$ 2 area. Performance was validated in a test $$\Sigma \Delta $$ Σ Δ Modulator with bandwidths of 200 kHz, 500 kHz and 2 MHz, and oversampling frequencies of 40, 60 and 80 MHz respectively, with negligible signal-to-noise ratio degradation compared to an ideal clock.

A High-Order Sigma-Delta Modulator Applied in Micro-Accelerometer

2014 ◽  
Vol 609-610 ◽  
pp. 1266-1270
Author(s):  
Jian Yang ◽  
Liang Liu ◽  
Qiu Ye Lv ◽  
Xiao Wei Liu ◽  
Liang Yin
Keyword(s):  
Noise Level ◽  
Signal To Noise Ratio ◽  
High Order ◽  
Signal Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Ideal Situation ◽  
Micro Accelerometer ◽  
The Ideal

In this paper a high-order sigma-delta modulator applied in micro-accelerometer is designed. The modulator chooses the distributed feedback structure. And the signal bandwidth is 500Hz, the oversampling ratio is 250 and sampling frequency is 250KHz. By the MATLAB Simulink simulation, when the input signal is 1g, and the signal frequency is 250Hz, the simulation result is that the noise level is-160dBV at the signal frequency in the ideal situation. And when considering the non-ideal factors, the simulation result shows that the noise level at the input accelerated signal is 20dBV higher than the ideal. The overall circuit was implemented under 0.5 um CMOS process and simulated in Cadence Spectre. The final simulation results show that the signal to noise ratio (SNR) is 97.1dB.

Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

2012 ◽  
Vol 503 ◽  
pp. 415-419 ◽  
Author(s):  
Wei Ping Chen ◽  
Qiang Fu ◽  
Xiao Wei Liu ◽  
Yan Xiao ◽  
Bin Zhang ◽  
...  
Keyword(s):  
High Precision ◽  
Sampling Rate ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Pass Band ◽  
Sigma Delta ◽  
Band Filter ◽  
Cic Filter ◽  
Decimation Filter ◽  
Sigma Delta Adc

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

scholarly journals A 77-GHz High Gain Low Noise Receiver for Automatic Radar Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1516
Author(s):  
Shuai Cheng ◽  
Linhong Li ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Receiver Design ◽  
Voltage Controlled Oscillator ◽  
Noise Amplifier ◽  
On Chip ◽  
77 Ghz

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

scholarly journals An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 1973
Author(s):  
Chunge Ju ◽  
Xiang Li ◽  
Junjun Zou ◽  
Qi Wei ◽  
Bin Zhou ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Input Signal ◽  
Continuous Time ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Sigma Delta ◽  
Mems Gyroscope ◽  
Auto Tuning ◽  
Σδ Modulator

This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.

A Sigma-Delta Modulator System Design with 1-1-1 Mash Structure

2013 ◽  
Vol 389 ◽  
pp. 568-572
Author(s):  
Ming Xin Song ◽  
Zhi Ming Wang ◽  
Yang Yang
Keyword(s):  
Simulation Model ◽  
System Design ◽  
Input Signal ◽  
Dynamic Range ◽  
Gain Coefficient ◽  
Process Conditions ◽  
Cmos Process ◽  
Audio Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta

This paper designs a three cascaded sigma-delta modulator with using mash structure. Analysis of gain coefficient of each module and simulate the modulator for the behavioral level. In 0.5μm CMOS process conditions, the input signal bandwidth is 20 kHz, oversampling rate is 256, SNR of the simulation model can get 100.5 dB, and accuracy is greater than 16 bit. Compared with other structures of the modulator, it has more stable and more dynamic range, so it can be applied to audio-frequency circuit.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

A Power-Efficient Noise Canceling Technique Using Signal-Suppression Feed-Forward for Wideband LNAs

2015 ◽  
Vol 643 ◽  
pp. 109-116
Author(s):  
Daiki Oki ◽  
Satoru Kawauchi ◽  
Cong Bing Li ◽  
Masataka Kamiyama ◽  
Seiichi Banba ◽  
...  
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Noise Figure ◽  
Wide Band ◽  
Noise Cancellation ◽  
Cmos Process ◽  
Feed Forward ◽  
Power Efficient ◽  
Signal Suppression ◽  
Noise Canceling

This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.

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