A High-Performance Full Adder Circuit Based on a Novel 7-T XOR-XNOR Cell

2013 ◽  
Vol 321-324 ◽  
pp. 361-366
Author(s):  
Yan Yu Ding ◽  
De Ming Wang ◽  
Qing Qing Huang ◽  
Hong Zhou Tan
Keyword(s):  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Full Adder ◽  
Path Delay ◽  
Feedback Path ◽  
Voltage Loss ◽  
Transmission Gates ◽  
Voltage Swing ◽  
Power Delay Product

A high performance full adder circuit with full voltage-swing based on a novel 7-transistor xor-xnor cell is proposed in this paper. In our design, we exploit a novel 7-transistor xor-xnor circuit with a signal level restorer in a feedback path to settle the threshold voltage loss problem. Then we present a new high-performance 1-bit full adder based on the designed xor-xnor cell, pass-transistors and transmission gates. The simulation results prove that, compared with other designs in literature, the proposed full adder shows its superiority for less power dissipation, lower critical path delay and smaller power-delay product, and still provides full voltage swing in all nodes of the circuit.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

2016 ◽  
Vol 5 (03) ◽  
pp. 07-12
Author(s):  
Prof. Amruta Bijwar
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Full Adder ◽  
Basic Component ◽  
Xnor Gate ◽  
Transmission Gates ◽  
Design Systems ◽  
Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Buffer for High Performance in CNT Based VLSI Interconnects

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick
Keyword(s):  
Integrated Circuits ◽  
Packing Density ◽  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Vlsi Interconnects ◽  
Performance Constraints ◽  
Interconnect Delay ◽  
Interconnect Optimization ◽  
Technology Nodes

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

2011 ◽  
Vol 20 (04) ◽  
pp. 641-655 ◽  
Author(s):  
REZA FAGHIH MIRZAEE ◽  
MOHAMMAD HOSSEIN MOAIYERI ◽  
HAMID KHORSAND ◽  
KEIVAN NAVI
Keyword(s):  
Power Consumption ◽  
Great Improvement ◽  
High Performance ◽  
Full Adder ◽  
Good Choice ◽  
Lower Power ◽  
Pvt Variations ◽  
Power Delay Product ◽  
Full Swing ◽  
Hspice Simulation

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

scholarly journals Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Ali Asghar ◽  
Muhammad Mazher Iqbal ◽  
Waqar Ahmed ◽  
Mujahid Ali ◽  
Husain Parvez ◽  
...  
Keyword(s):  
High Performance ◽  
Critical Path ◽  
Path Delay ◽  
Gate Arrays ◽  
Area Reduction ◽  
Area Overhead ◽  
Logic Block ◽  
Field Programmable ◽  
Boolean Matching ◽  
Programmable Gate Arrays

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

scholarly journals High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

VLSI Design ◽  
2002 ◽  
Vol 15 (1) ◽  
pp. 417-426 ◽  
Author(s):  
Shen-Fu Hsiao ◽  
Jia-Siang Yeh ◽  
Da-Yen Chen
Keyword(s):  
Boolean Functions ◽  
High Performance ◽  
Voltage Drop ◽  
Critical Path ◽  
Logic Synthesis ◽  
Path Delay ◽  
Minimum Width ◽  
Pass Transistor ◽  
Pass Transistor Logic ◽  
Function Sharing

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

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