Study of threshold voltage fluctuation caused by source and drain extensions doping variation of tri-gate fin-type FET using three-dimensional device simulation

2014 ◽  
Vol 53 (6S) ◽  
pp. 06JE06 ◽  
Author(s):  
Toshiyuki Tsutsumi ◽  
Jaeyup Lee
2011 ◽  
Vol 470 ◽  
pp. 214-217
Author(s):  
Toshiro Hiramoto ◽  
Takuya Saraya ◽  
Chi Ho Lee

The threshold voltage (Vth) variability in fully depleted SOI MOSFETs with intrinsic channel and ultrathin buried oxide under back bias voltage (Vbs) is extensively investigated by three dimensional device simulation. It is found that the Vth variability increases only slightly by applying negative Vbs by the effect of random dopant fluctuation (RDF) in the substrate, while the Vth variability is severely degraded by applying positive Vbs by the effect of the back interface inversion. As a result, there is a certain value of Vbs around 0 V where the Vth variability is minimized.


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